MT53E1G32D2FW-046 WT:B

Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM Features LPDDR4X/LPDDR4 SDRAM MT53E512M32D1, MT53E1G32D2, MT53E512M64D2 Features • Single-ended CK and DQS support This data sheet is for LPDDR4X and LPDDR4 unified product based on LPDDR4X information. As for LPDDR4 setting, refer to General LPDDR4 Specification at the end of this data sheet. Options Marking • VDD1/VDD2/VDDQ: 1.80V/1.10V/0.60V or 1.10V • Array configuration – 512 Meg x 32 (2 channels x 16 I/O) – 1 Gig x 32 (2 channels x 16 I/O) – 512 Meg x 64 (4 channels x 16 I/O) • Device configuration – 512M32 x 1 die in package – 512M32 x 2 die in package • FBGA “green” package – 200-ball TFBGA (10mm × 14.5mm x 1.05mm, Ø0.40 SMD) – 200-ball TFBGA (10mm × 14.5mm x 1.1mm, Ø0.40 SMD) – 376-ball WFBGA (14mm × 14mm x 0.71mm, Ø0.24 SMD) – 556-ball TFBGA (12.4mm × 12.4mm x 1.1mm, Ø0.24 SMD) • Speed grade, cycle time – 468ps @ RL = 36/40 • Operating temperature range – –25°C to +85°C – –40°C to +95°C • Revision • Ultra-low-voltage core and I/O power supplies – VDD1 = 1.70–1.95V; 1.80V nominal – VDD2 = 1.06–1.17V; 1.10V nominal – VDDQ = 0.57–0.65V; 0.60V nominal or VDDQ = 1.06–1.17V; 1.10V nominal • Frequency range – 2133–10 MHz (data rate range per pin: 4266–20 Mb/s) • 16n prefetch DDR architecture • 8 internal banks per channel for concurrent operation • Single-data-rate CMD/ADR entry • Bidirectional/differential data strobe per byte lane • Programmable READ and WRITE latencies (RL/WL) • Programmable and on-the-fly burst lengths (BL = 16, 32) • Directed per-bank refresh for concurrent bank operation and ease of command scheduling • Up to 8.5 GB/s per die x16 channel • On-chip temperature sensor to control self refresh rate • Partial-array self refresh (PASR) • Selectable output drive strength (DS) • Clock-stop capability • RoHS-compliant, “green” packaging • Programmable VSS (ODT) termination E 512M32 1G32 512M64 D1 D2 ZW FW NZ HJ -046 WT IT :B Table 1: Key Timing Parameters WRITE Latency Clock Rate (MHz) Data Rate per Pin (Mb/s) Array Configuration Set A -046 2133 4266 512 Meg x 32 -046 2133 4266 -046 2133 4266 Speed Grade CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN READ Latency Set B DBI Disabled DBI Enabled 18 34 36 40 1G x 32 18 34 36 40 512 Meg x 64 18 34 36 40 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM Part Number Ordering Information Part Number Ordering Information Figure 1: Part Number Chart MT 53 E 512M32 D1 ZW -046 WT Micron Technology :B Design Revision :B Product Family 53 = Mobile LPDDR4 SDRAM Operating Temperature Operating Voltage WT = –25°C to +85°C IT = –40°C to +95°C E = 1.10V V DD2 / 0.60V VDDQ or 1.10V VDDQ Automotive Certification (option) A = Package-level burn-in (Blank) = Standard Configuration 512M32 = 512 Meg x 32 1G32 = 1 Gig x 32 512M64 = 512 Meg x 64 Cycle Time -046 = 468ps, tCK RL = 36/40 Addressing Package Codes D1 = LPDDR4, 1 die D2 = LPDDR4, 2 die ZW = 200-ball TFBGA 10 x 14.5 x 1.05mm (Ø0.40 SMD) FW = 200-ball TFBGA 10 x 14.5 x 1.1mm (Ø0.40 SMD) NZ = 376-ball WFBGA 14 x 14 x 0.71mm (Ø0.24 SMD) HJ = 556-ball TFBGA 12.4 x 12.4 x 1.1mm (Ø0.24 SMD) Table 2: Part Number List Total Density Data Rate per Pin MT53E512M32D1ZW-046 WT:B Part Number 2GB (16Gb) 4266 Mb/s MT53E512M32D1ZW-046 IT:B 2GB (16Gb) 4266 Mb/s MT53E1G32D2FW-046 WT:B 4GB (32Gb) 4266 Mb/s MT53E512M64D2NZ-046 WT:B 4GB (32Gb) 4266 Mb/s MT53E512M64D2HJ-046 WT:B 4GB (32Gb) 4266 Mb/s FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM Contents Part Number Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 FBGA Part Marking Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Important Notes and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Product Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Refresh Requirement Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ball Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Ball Descriptions and Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Product Specific Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 IDD Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 IDD Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 General LPDDR4X Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SDRAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Simplified Bus Interface State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Power-Up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Voltage Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Reset Initialization with Stable Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Power-Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Controlled Power-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Uncontrolled Power-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Mode Register Assignments and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Commands and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ACTIVATE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Read and Write Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Preamble and Postamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 t LZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Burst WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 tWPRE Calculation for ATE (Automatic Test Equipment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 t WPST Calculation for ATE (Automatic Test Equipment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 MASK WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Mask Write Timing Constraints for BL16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Data Mask and Data Bus Inversion (DBI [DC]) Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 WRITE and MASKED WRITE Operation DQS Control (WDQS Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 WDQS Control Mode 1 – Read-Based Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 WDQS Control Mode 2 – WDQS_On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Preamble and Postamble Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Preamble, Postamble Behavior in READ-to-READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM READ-to-READ Operations – Seamless . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 READ-to-READ Operations – Consecutive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 WRITE-to-WRITE Operations – Seamless . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 WRITE-to-WRITE Operations – Consecutive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 PRECHARGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Burst READ Operation Followed by Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Burst WRITE Followed by Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Burst READ With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Burst WRITE With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 RAS Lock Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Delay Time From WRITE-to-READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Burst READ Operation Followed by Per-Bank Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Refresh Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Refresh Management Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Refresh Management Command Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Refresh Management Operation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SELF REFRESH Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Self Refresh Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Power-Down Entry and Exit During Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Command Input Timing After Power-Down Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Self Refresh Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 MRR, MRW, MPC Commands During tXSR, tRFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Power-Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Input Clock Stop and Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Clock Frequency Change – CKE LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Clock Stop – CKE LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Clock Frequency Change – CKE HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Clock Stop – CKE HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 MODE REGISTER READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 MRR After a READ and WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 MRR After Power-Down Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 MODE REGISTER WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Mode Register Write States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 VREF Current Generator (VRCG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 VREF Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 VREF(CA) Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 VREF(DQ) Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Command Bus Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Command Bus Training Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Training Sequence for Single-Rank Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Training Sequence for Multiple-Rank Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Relation Between CA Input Pin and DQ Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Mode Register Write-WR Leveling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Write Leveling Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Input Clock Frequency Stop and Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 MULTIPURPOSE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Read DQ Calibration Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Read DQ Calibration Training Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Read DQ Calibration Training Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM MPC[READ DQ CALIBRATION] After Power-Down Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Write Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Internal Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 DQS Interval Oscillator Matching Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 OSC Count Readout Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Thermal Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 ZQ Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 ZQCAL Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Multichannel Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 ZQ External Resistor, Tolerance, and Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Frequency Set Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Frequency Set Point Update Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Pull-Up and Pull-Down Characteristics and Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 On-Die Termination for the Command/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 ODT Mode Register and ODT State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 ODT Mode Register and ODT Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 ODT for CA Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 DQ On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Output Driver and Termination Register Temperature and Voltage Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 ODT Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Asynchronous ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 DQ ODT During Power-Down and Self Refresh Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 ODT During Write Leveling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Target Row Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 TRR Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Post-Package Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Failed Row Address Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Read Preamble Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 AC and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 AC and DC Input Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Input Levels for CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Input Levels for RESET_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Differential Input Voltage for CK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Peak Voltage Calculation Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Single-Ended Input Voltage for Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Differential Input Slew Rate Definition for Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Differential Input Cross-Point Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Differential Input Voltage for DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Peak Voltage Calculation Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Single-Ended Input Voltage for DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Differential Input Slew Rate Definition for DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Differential Input Cross-Point Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Input Levels for ODT_CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Output Slew Rate and Overshoot/Undershoot Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Single-Ended Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Differential Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Overshoot and Undershoot Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Driver Output Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 LVSTL I/O System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Input/Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM IDD Specification Parameters and Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 IDD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 CA Rx Voltage and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 DQ Tx Voltage and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 DRAM Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 DQ Rx Voltage and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 tCK(abs), tCH(abs), and tCL(abs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Clock Period Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Clock Period Jitter Effects on Core Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Cycle Time Derating for Core Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Clock Cycle Derating for Core Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Clock Jitter Effects on Command/Address Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Clock Jitter Effects on READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Clock Jitter Effects on WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 LPDDR4 1.10V VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Power-Up and Initialization - LPDDR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Mode Register Definition - LPDDR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Burst READ Operation - LPDDR4 ATE Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 t LZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 VREF Specifications - LPDDR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Internal VREF(CA) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Internal VREF(DQ) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Command Definitions and Timing Diagrams - LPDDR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Pull Up/Pull Down Driver Characteristics and Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 On-Die Termination for the Command/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 ODT Mode Register and ODT State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 ODT Mode Register and ODT Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 DQ On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Output Driver and Termination Register Temperature and Voltage Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 AC and DC Operating Conditions - LPDDR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Output Slew Rate and Overshoot/Undershoot specifications - LPDDR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Single-Ended Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Differential Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 LVSTL I/O System - LPDDR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Product Specific Mode Register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Rev. G – 05/2022 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Rev. F – 04/2022 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Rev. E – 02/2022 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Rev. D – 11/2021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Rev. C – 09/2021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Rev. B – 05/2021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Rev. A – 04/2021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM List of Figures Figure 1: Part Number Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 2: Single-Die, Dual-Channel Package Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 3: Dual-Die, Dual-Channel Package Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4: Dual-Die, Quad-Channel Package Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 5: 200-Ball Dual-Channel, Single-Rank Discrete FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 6: 200-Ball Dual-Channel, Dual-Rank Discrete FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 7: 376-Ball Quad-Channel, Single-Rank POP FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 8: 556-Ball Quad-Channel, Single-Rank POP FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 9: 200-Ball TFBGA – 10mm x 14.5mm x 1.05mm (Package Code: ZW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 10: 200-Ball TFBGA – 10mm x 14.5mm x 1.1mm (Package Code: FW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 11: 376-Ball WFBGA – 14.0mm x 14.0mm x 0.71mm (Package Code: NZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 12: 556-Ball TFBGA – 12.4mm x 12.4mm x 1.1mm (Package Code: HJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 13: Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 14: Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 15: Voltage Ramp and Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 16: ACTIVATE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 17: tFAW Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 18: DQS Read Preamble and Postamble – Toggling Preamble and 0.5nCK Postamble . . . . . . . . . . . . . . . . . . . 79 Figure 19: DQS Read Preamble and Postamble – Static Preamble and 1.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . 79 Figure 20: DQS Write Preamble and Postamble – 0.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 21: DQS Write Preamble and Postamble – 1.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 22: Burst Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 23: Burst Read Followed by Burst Write or Burst Mask Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 24: Seamless Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 25: Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 26: tLZ(DQS) Method for Calculating Transitions and Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 27: tHZ(DQS) Method for Calculating Transitions and Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 28: tLZ(DQ) Method for Calculating Transitions and Endpoint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 29: tHZ(DQ) Method for Calculating Transitions and Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 30: Burst WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 31: Burst Write Followed by Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 32: Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 33: Method for Calculating tWPRE Transitions and Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 34: Method for Calculating tWPST Transitions and Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 35: MASK WRITE Command – Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 36: MASK WRITE Command – Different Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 37: MASKED WRITE Command with Write DBI Enabled; DM Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 38: WRITE Command with Write DBI Enabled; DM Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 39: WDQS Control Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 40: Burst WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 41: Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Disable) . . . . . . . . . . . . . . . . . . . . 103 Figure 42: Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Enable) . . . . . . . . . . . . . . . . . . . . 103 Figure 43: READ Operations: tCCD = MIN, Preamble = Toggle, 1.5nCK Postamble. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 44: Seamless READ: tCCD = MIN + 1, Preamble = Toggle, 1.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 45: Consecutive READ: tCCD = MIN + 1, Preamble = Toggle, 0.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 46: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 1.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 47: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 0.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 48: Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 1.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 49: Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 0.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 50: Consecutive READ: tCCD = MIN + 2, Preamble = Static, 1.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 51: Consecutive READ: tCCD = MIN + 2, Preamble = Static, 0.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . . 108 CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM Figure 52: Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 1.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 53: Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 0.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 54: Consecutive READ: tCCD = MIN + 3, Preamble = Static, 1.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 55: Consecutive READ: tCCD = MIN + 3, Preamble = Static, 0.5nCK Postamble . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 56: Seamless WRITE: tCCD = MIN, 0.5nCK Postamble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 57: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble, 533 MHz < Clock Frequency ) Upper Frequency Limit(≤) Units Notes 6 6 4 4 6 8 10 266 MHz 1–6 10 12 6 8 10 8 266 533 14 16 8 12 16 8 533 800 20 22 10 18 20 8 800 1066 24 28 12 22 24 10 1066 1333 28 32 14 26 30 12 1333 1600 32 36 16 30 34 14 1600 1866 36 40 18 34 40 16 1866 2133 Notes: 1. The device should not be operated at a frequency above the upper frequency limit or below the lower frequency limit shown for each RL, WL, or nWR value. 2. DBI for READ operations is enabled in MR3 OP[6]. When MR3 OP[6] = 0, then the "No DBI" column should be used for READ latency. When MR3 OP[6] = 1, then the "w/DBI" column should be used for READ latency. 3. WRITE latency set A and set B are determined by MR2 OP[6]. When MR2 OP[6] = 0, then WRITE latency set A should be used. When MR2 OP[6] = 1, then WRITE latency set B should be used. 4. The programmed value for nRTP is the number of clock cycles the device uses to determine the starting point of an internal PRECHARGE operation after a READ burst with AP (auto precharge) enabled . It is determined by RU(tRTP/tCK). 5. The programmed value of nWR is the number of clock cycles the device uses to determine the starting point of an internal PRECHARGE operation after a WRITE burst with AP (auto precharge) enabled. It is determined by RU(tWR/tCK). 6. nRTP shown in this table is valid for BL16 only. For BL32, the device will add 8 clocks to the nRTP value before starting a precharge. Table 30: MR3 I/O Configuration 1 (MA[5:0] = 03h) OP7 OP6 DBI-WR DBI-RD CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN OP5 OP4 OP3 PDDS 56 OP2 OP1 OP0 PPRP WR-PST PU-CAL Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 31: MR3 Op-Code Bit Definitions Feature PU-CAL (Pull-up calibration point) Type OP Write-only OP[0] WR-PST (WR postamble length) OP[1] PPRP (Post-package repair protection) OP[2] PDDS (Pull-down drive strength) OP[5:3] Definition Notes 0b: VDDQ × 0.6 1–4 1b: VDDQ × 0.5 (default) 0b: WR postamble = 0.5 × tCK (default) 1b: WR postamble = 1.5 × tCK 0b: PPR protection disabled (default) 2, 3, 5 6 1b: PPR protection enabled 000b: RFU 1, 2, 3 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 (default) 111b: Reserved DBI-RD (DBI-read enable) OP[6] DBI-WR (DBI-write enable) OP[7] 0b: Disabled (default) 2, 3 1b: Enabled 0b: Disabled (default) 2, 3 1b: Enabled Notes: 1. All values are typical. The actual value after calibration will be within the specified tolerance for a given voltage and temperature. Recalibration may be required as voltage and temperature vary. 2. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1.The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. 4. For dual-channel device, PU-CAL (MR3-OP[0]) must be set the same for both channels on a die. The SDRAM will read the value of only one register (Ch.A or Ch.B); the choice is vendor-specific, so both channels must be set the same. 5. 1.5 × tCK apply > 1.6 GHz clock. 6. If MR3 OP[2] is set to 1b, PPR protection mode is enabled. The PPR protection bit is a sticky bit and can only be set to 0b by a power on reset. MR4 OP[4] controls entry to PPR mode. If PPR protection is enabled then the DRAM will not allow writing of 1b to MR4 OP[4]. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 32: MR4 Device Temperature (MA[5:0] = 04h) OP7 OP6 TUF OP5 Thermal offset OP4 OP3 PPRE SR abort OP2 OP1 OP0 Refresh rate Table 33: MR4 Op-Code Bit Definitions Feature Refresh rate Type OP Read-only OP[2:0] Definition Notes 000b: SDRAM low temperature operating limit exceeded 1–4, 7–9 001b: 4x refresh 010b: 2x refresh 011b: 1x refresh (default) 100b: 0.5x refresh 101b: 0.25x refresh, no derating 110b: 0.25x refresh, with derating 111b: SDRAM high temperature operating limit exceeded SR abort (Self refresh abort) Write PPRE (Post-package repair entry/exit) Write Thermal offset-controller offset to TCSR Write OP[3] 0b: Disable (default) 9 1b: Device dependent OP[4] 0b: Exit PPR mode (default) 5, 9 1b: Enter PPR mode (Reference MR25 OP[7:0] for available PPR resources) OP[6:5] 00b: No offset, 0–5°C gradient (default) 9 01b: 5°C offset, 5–10°C gradient 10b: 10°C offset, 10–15°C gradient 11b: Reserved TUF (Temperature update flag) Read-only OP7 0b: OP[2:0] No change in OP[2:0] since last MR4 read (default) 6–8 1b: Change in OP[2:0] since last MR4 read Notes: 1. The refresh rate for each MR4 OP[2:0] setting applies to tREFI, tREFIpb, and tREFW. MR4 OP[2:0] = 011b corresponds to a device temperature of 85°C. Other values require either a longer (2x, 4x) refresh interval at lower temperatures or a shorter (0.5x, 0.25x) refresh interval at higher temperatures. If MR4 OP[2] = 1b, the device temperature is greater than 85°C. 2. At higher temperatures (>85°C), AC timing derating may be required. If derating is required the device will set MR4 OP[2:0] = 110b. See derating timing requirements in the AC Timing section. 3. DRAM vendors may or may not report all of the possible settings over the operating temperature range of the device. Each vendor guarantees that their device will work at any temperature within the range using the refresh interval requested by their device. 4. The device may not operate properly when MR4 OP[2:0] = 000b or 111b. 5. Post-package repair can be entered or exited by writing to MR4 OP[4]. 6. When MR4 OP[7] = 1b, the refresh rate reported in MR4 OP[2:0] has changed since the last MR4 read. A mode register read from MR4 will reset MR4 OP[7] to 0b. 7. MR4 OP[7] = 0b at power-up. MR4 OP[2:0] bits are valid after initialization sequence (Te). 8. See the Temperature Sensor section for information on the recommended frequency of reading MR4. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification 9. MR4 OP[6:3] can be written in this register. All other bits will be ignored by the device during an MRW command to this register. Table 34: MR5 Basic Configuration 1 (MA[5:0] = 05h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP2 OP1 OP0 OP2 OP1 OP0 Manufacturer ID Table 35: MR5 Op-Code Bit Definitions Feature Manufacturer ID Type OP Read-only OP[7:0] Definition 1111 1111b: Micron All others: Reserved Table 36: MR6 Basic Configuration 2 (MA[5:0] = 06h) OP7 OP6 OP5 OP4 OP3 Revision ID1 Note: 1. MR6 is vendor-specific. Table 37: MR6 Op-Code Bit Definitions Feature Revision ID1 Type OP Read-only OP[7:0] Definition xxxx xxxxb: Revision ID1 Note: 1. MR6 is vendor-specific. Table 38: MR7 Basic Configuration 3 (MA[5:0] = 07h) OP7 OP6 OP5 OP4 OP3 Revision ID2 Table 39: MR7 Op-Code Bit Definitions Feature Revision ID2 Type OP Read-only OP[7:0] Definition xxxx xxxxb: Revision ID2 Note: 1. MR7 is vendor-specific. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 40: MR8 Basic Configuration 4 (MA[5:0] = 08h) OP7 OP6 OP5 OP4 I/O width OP3 OP2 OP1 Density OP0 Type Table 41: MR8 Op-Code Bit Definitions Feature Type Type OP Read-only OP[1:0] Definition 00b: S16 SDRAM (16n prefetch) All others: Reserved Density Read-only OP[5:2] 0000b: 4Gb dual-channel die/2Gb single-channel die 0001b: 6Gb dual-channel die/3Gb single-channel die 0010b: 8Gb dual-channel die/4Gb single-channel die 0011b: 12Gb dual-channel die/6Gb single-channel die 0100b: 16Gb dual-channel die/8Gb single-channel die 0101b: 24Gb dual-channel die/12Gb single-channel die 0110b: 32Gb dual-channel die/16Gb single-channel die 1100b: 2Gb dual-channel die/1Gb single-channel die All others: Reserved I/O width Read-only OP[7:6] 00b: x16/channel 01b: x8/channel All others: Reserved Table 42: MR9 Test Mode (MA[5:0] = 09h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Vendor-specific test mode Table 43: MR9 Op-Code Definitions Feature Test mode Type OP Write-only OP[7:0] Definition 0000000b; Vendor-specific test mode disabled (default) Table 44: MR10 Calibration (MA[5:0] = 0Ah) OP7 OP6 OP5 OP4 OP3 OP2 RFU OP1 OP0 ZQ RESET Table 45: MR10 Op-Code Bit Definitions Feature Type OP ZQ reset Write-only OP[0] Definition 0b: Normal operation (default) 1b: ZQ reset Notes: 1. See AC Timing table for calibration latency and timing. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification 2. If ZQ is connected to VDDQ through RZQ, either the ZQ CALIBRATION function or default calibration (via ZQ reset) is supported. If ZQ is connected to VSS, the device operates with default calibration and ZQ CALIBRATION commands are ignored. In both cases, the ZQ connection must not change after power is supplied to the device. Table 46: MR11 ODT Control (MA[5:0] = 0Bh) OP7 OP6 OP5 RFU OP4 OP3 CA ODT OP2 RFU OP1 OP0 DQ ODT Table 47: MR11 Op-Code Bit Definitions Feature DQ ODT DQ bus receiver on-die termination Type OP Write-only OP[2:0] Definition Notes 000b: Disable (default) 1, 2, 3 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 111b: RFU CA ODT CA bus receiver on-die termination Write-only OP[6:4] 000b: Disable (default) 1, 2, 3 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 111b: RFU Notes: 1. All values are typical. The actual value after calibration will be within the specified tolerance for a given voltage and temperature. Re-calibration may be required as voltage and temperature vary. 2. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation. Table 48: MR12 Register Information (MA[5:0] = 0Ch) OP7 OP6 RFU VRCA CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN OP5 OP4 OP3 OP2 OP1 OP0 VREF(CA) 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 49: MR12 Op-Code Bit Definitions Feature Type OP Data VREF(CA) VREF(CA) settings Read/Write OP[5:0] VRCA VREF(CA) range Read/Write Notes 000000b–110010b: See VREF Settings table 1–3, 5, 6 All others: Reserved OP[6] 0b: VREF(CA) range[0] enabled 1, 2, 4, 5, 6 1b: VREF(CA) range[1] enabled (default) Notes: 1. This register controls the VREF(CA) levels for frequency set point[1:0]. Values from either VR(ca)[0] or VR(ca)[1] may be selected by setting MR12 OP[6] appropriately. 2. A read to MR12 places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ will be set to 0. See the MRR Operation section. 3. A write to MR12 OP[5:0] sets the internal VREF(CA) level for FSP[0] when MR13 OP[6] = 0b or sets the internal VREF(CA) level for FSP[1] when MR13 OP[6] = 1b. The time required for VREF(CA) to reach the set level depends on the step size from the current level to the new level. See the VREF(CA) training section. 4. A write to MR12 OP[6] switches the device between two internal VREF(CA) ranges. The range (range[0] or range[1]) must be selected when setting the VREF(CA) register. The value, once set, will be retained until overwritten or until the next power-on or reset event. 5. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 6. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. Table 50: MR13 Register Control (MA[5:0] = 0Dh) OP[7] OP[6] OP[5] OP[4] OP[3] OP[2] OP[1] OP[0] FSP-OP FSP-WR DMD RRO VRCG VRO RPT CBT CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 51: MR13 Op-Code Bit Definition Feature CBT Command bus training Type OP Write-only OP[0] Definition Notes 0b: Normal operation (default) 1 1b: Command bus training mode enabled RPT Read preamble training OP[1] VRO VREF output OP[2] VRCG VREF current generator OP[3] RRO Refresh rate option OP[4] DMD Data mask disable OP[5] FSP-WR Frequency set point write/read OP[6] FSP-OP FREQUENCY SET POINT operation mode OP[7] 0b: Disabled (default) 1b: Read preamble training mode enabled 0b: Normal operation (default) 2 1b: Output the VREF(CA) and VREF(DQ) values on DQ bits 0b: Normal operation (default) 3 1b: Fast response (high current) mode 0b: Disable codes 001 and 010 in MR4 OP[2:0] 4, 5 1b: Enable all codes in MR4 OP[2:0] 0b: DATA MASK operation enabled (default) 6 1b: DATA MASK operation disabled 0b: Frequency set point[0] (default) 7 1b: Frequency set point[1] 0b: Frequency set point[0] (default) 8 1b: Frequency set point[1] Notes: 1. A write to set OP[0] = 1 causes the LPDDR4 SDRAM to enter the command bus training mode. When OP[0] = 1 and CKE goes LOW, commands are ignored and the contents of CA[5:0] are mapped to the DQ bus. CKE must be brought HIGH before doing a MRW to clear this bit (OP[0] = 0) and return to normal operation. See the Command Bus Training section for more information. 2. When set, the device will output the VREF(CA) and VREF(DQ) voltage on DQ pins. Only the "active" frequency set point, as defined by MR13 OP[7], will be output on the DQ pins. This function allows an external test system to measure the internal V REF levels. The DQ pins used for VREF output are vendor-specific. 3. When OP[3] = 1, the VREF circuit uses a high current mode to improve VREF settling time. 4. MR13 OP[4] RRO bit is valid only when MR0 OP[0] = 1. For LPDDR4 SDRAM with MR0 OP[0] = 0, MR4 OP[2:0] bits are not dependent on MR13 OP[4]. 5. When OP[4] = 0, only 001b and 010b in MR4 OP[2:0] are disabled. LPDDR4 SDRAM must report 011b instead of 001b or 010b in this case. Controller should follow the refresh mode reported by MR4 OP[2:0], regardless of RRO setting. TCSR function does not depend on RRO setting. 6. When enabled (OP[5] = 0b) data masking is enabled for the device. When disabled (OP[5] = 1b), the device will ignore any mask patterns issued during a MASKED WRITE command. See the Data Mask section for more information. 7. FSP-WR determines which frequency set point registers are accessed with MRW and MRR commands for the following functions such as VREF(CA) setting, VREF(CA) range, VREF(DQ) setting, VREF(DQ) range. For more information, refer to Frequency Set Point section. 8. FSP-OP determines which frequency set point register values are currently used to specify device operation for the following functions such as V REF(CA) setting, VREF(CA) range, VREF(DQ) setting, VREF(DQ) range. For more information, refer to Frequency Set Point section. Table 52: Mode Register 14 (MA[5:0] = 0Eh) OP[7] OP[6] RFU VRDQ CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN OP[5] OP[4] OP[3] OP[2] OP[1] OP[0] VREF(DQ) 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 53: MR14 Op-Code Bit Definition Feature VREF(DQ) VREF(DQ) setting Type OP Read/Write OP[5:0] VRDQ VREF(DQ) range Definition Notes 000000b–110010b: See VREF Settings table 1–3, 5, 6 All others: Reserved OP[6] 0b: VREF(DQ) range[0] enabled 1, 2, 4–6 1b: VREF(DQ) range[1] enabled (default) Notes: 1. This register controls the VREF(DQ) levels for frequency set point[1:0]. Values from either VRDQ[0] (vendor defined) or VRDQ[1] (vendor defined) may be selected by setting OP[6] appropriately. 2. A read (MRR) to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ shall be set to 0. See the MRR Operation section. 3. A write to OP[5:0] sets the internal VREF(DQ) level for FSP[0] when MR13 OP[6] = 0b, or sets FSP[1] when MR13 OP[6] = 1b. The time required for VREF(DQ) to reach the set level depends on the step size from the current level to the new level. See the VREF(DQ) training section. 4. A write to OP[6] switches the device between two internal VREF(DQ) ranges. The range (range[0] or range[1]) must be selected when setting the VREF(DQ) register. The value, once set, will be retained until overwritten, or until the next power-on or reset event. 5. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 6. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 54: VREF Setting for Range[0] and Range[1] Function OP Range[0] Values Range[1] Values VREF(CA) (% of VDDQ) VREF(DQ) (% of VDDQ) VREF setting for MR12 and MR14 OP[5:0] VREF(CA) (% of VDDQ) VREF(DQ) (% of VDDQ) 000000b: 15.0% 011010b: 30.5% 000000b: 32.9% 011010b: 48.5% 000001b: 15.6% 011011b: 31.1% 000001b: 33.5% 011011b: 49.1% 000010b: 16.2% 011100b: 31.7% 000010b: 34.1% 011100b: 49.7% 000011b: 16.8% 011101b: 32.3% 000011b: 34.7% 011101b: 50.3% (default) 000100b: 17.4% 011110b: 32.9% 000100b: 35.3% 011110b: 50.9% 000101b: 18.0% 011111b: 33.5% 000101b: 35.9% 011111b: 51.5% 000110b: 18.6% 100000b: 34.1% 000110b: 36.5% 100000b: 52.1% 000111b: 19.2% 100001b: 34.7% 000111b: 37.1% 100001b: 52.7% 001000b: 19.8% 100010b: 35.3% 001000b: 37.7% 100010b: 53.3% 001001b: 20.4% 100011b: 35.9% 001001b: 38.3% 100011b: 53.9% 001010b: 21.0% 100100b: 36.5% 001010b: 38.9% 100100b: 54.5% 001011b: 21.6% 100101b: 37.1% 001011b: 39.5% 100101b: 55.1% 001100b: 22.2% 100110b: 37.7% 001100b: 40.1% 100110b: 55.7% 001101b: 22.8% 100111b: 38.3% 001101b: 40.7% 100111b: 56.3% 001110b: 23.4% 101000b: 38.9% 001110b: 41.3% 101000b: 56.9% 001111b: 24.0% 101001b: 39.5% 001111b: 41.9% 101001b: 57.5% 010000b: 24.6% 101010b: 40.1% 010000b: 42.5% 101010b: 58.1% 010001b: 25.1% 101011b: 40.7% 010001b: 43.1% 101011b: 58.7% 010010b: 25.7% 101100b: 41.3% 010010b: 43.7% 101100b: 59.3% 010011b: 26.3% 101101b: 41.9% 010011b: 44.3% 101101b: 59.9% 010100b: 26.9% 101110b: 42.5% 010100b: 44.9% 101110b: 60.5% 010101b: 27.5% 101111b: 43.1% 010101b: 45.5% 101111b: 61.1% 010110b: 28.1% 110000b: 43.7% 010110b: 46.1% 110000b: 61.7% 010111b: 28.7% 110001b: 44.3% 010111b: 46.7% 110001b: 62.3% 011000b: 29.3% 110010b: 44.9% 011000b: 47.3% 110010b: 62.9% 011001b: 29.9% All others: Reserved 011001b: 47.9% All others: Reserved Notes: 1. These values may be used for MR14 OP[5:0] and MR12 OP[5:0] to set the VREF(CA) or VREF(DQ) levels in the device. 2. The range may be selected in each of the MR14 or MR12 registers by setting OP[6] appropriately. 3. Each of the MR14 or MR12 registers represents either FSP[0] or FSP[1]. Two frequency set points each for CA and DQ are provided to allow for faster switching between terminated and unterminated operation or between different high-frequency settings, which may use different terminations values. 4. Notes 1–3 apply to entire table. Table 55: MR15 Register Information (MA[5:0] = 0Fh) OP[7] OP[6] OP[5] OP[4] OP[3] OP[2] OP[1] OP[0] Lower-byte invert register for DQ calibration CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 56: MR15 Op-code Bit Definition Feature Lower-byte invert for DQ calibration Type OP Definition Write-only OP[7:0] Notes The following values may be written for any operand OP[7:0] and will be applied to the corresponding DQ locations DQ[7:0] within a byte lane 1–3 0b: Do not invert 1b: Invert the DQ calibration patterns in MR32 and MR40 Default value for OP[7:0] = 55h Notes: 1. This register will invert the DQ calibration pattern found in MR32 and MR40 for any single DQ or any combination of DQ. Example: If MR15 OP[7:0] = 00010101b, then the DQ calibration patterns transmitted on DQ[7, 6, 5, 3, 1] will not be inverted, but the DQ calibration patterns transmitted on DQ[4, 2, 0] will be inverted. 2. DM[0] is not inverted and always transmits the "true" data contained in MR32 and MR40. 3. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3-OP[6]. Table 57: MR15 Invert Register Pin Mapping PIN DQ0 DQ1 DQ2 DQ3 DMIO DQ4 DQ5 DQ6 DQ7 MR15 OP0 OP1 OP2 OP3 No invert OP4 OP5 OP6 OP7 Table 58: MR16 PASR Bank Mask (MA[5:0] = 010h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 PASR bank mask Table 59: MR16 Op-Code Bit Definitions Feature Bank[7:0] mask Type OP Write-only OP[7:0] Definition 0b: Bank refresh enabled (default) 1b: Bank refresh disabled OP[n] Bank Mask 8-Bank SDRAM 0 xxxxxxx1 Bank 0 1 xxxxxx1x Bank 1 2 xxxxx1xx Bank 2 3 xxxx1xxx Bank 3 4 xxx1xxxx Bank 4 5 xx1xxxxx Bank 5 6 x1xxxxxx Bank 6 7 1xxxxxxx Bank 7 Notes: 1. When a mask bit is asserted (OP[n] = 1), refresh to that bank is disabled. 2. PASR bank masking is on a per-channel basis; the two channels on the die may have different bank masking in dual-channel devices. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 60: MR17 PASR Segment Mask (MA[5:0] = 11h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 PASR segment mask Table 61: MR17 PASR Segment Mask Definitions Feature Segment[7:0] mask Type OP Definition Write-only OP[7:0] 0b: Segment refresh enabled (default) 1b: Segment refresh disabled Table 62: MR17 PASR Segment Mask Density (per channel) 1Gb 2Gb 3Gb 4Gb 6Gb 8Gb 12Gb 16Gb R[12:10] R[13:11] R[14:12] R[14:12] R[15:13] R[15:13] R[16:14] R[16:14] 110b Not allowed 110b Segm ent OP Segment Mask 0 0 XXXXXXX1 000b 1 1 XXXXXX1X 001b 2 2 XXXXX1XX 010b 3 3 XXXX1XXX 011b 4 4 XXX1XXXX 100b 5 5 XX1XXXXX 101b 6 6 X1XXXXXX 110b 110b 7 7 1XXXXXXX 111b 111b Not allowed 110b 111b Not allowed 111b 111b Notes: 1. This table indicates the range of row addresses in each masked segment. "X" is “Don’t Care” for a particular segment. 2. PASR segment-masking is on a per-channel basis. The two channels on the die may have different segment masking in dual-channel devices. 3. For 3Gb, 6Gb, and 12Gb density per channel, OP[7:6] must always be LOW (= 00b). Table 63: MR18 Register Information (MA[5:0] = 12h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQS oscillator count - LSB Table 64: MR18 LSB DQS Oscillator Count Function Type DQS oscillator count Read-only (WR training DQS oscillator) OP OP[7:0] Definition 0h–FFh LSB DRAM DQS oscillator count Notes: 1. MR18 reports the LSB bits of the DRAM DQS oscillator count. The DRAM DQS oscillator count value is used to train DQS to the DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically adjust the phase of DQS relative to DQ. 2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS oscillator count. 3. The value in this register is reset each time an MPC command is issued to start in the DQS oscillator counter. 4. Notes 1–3 apply to entire table. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 65: MR19 Register Information (MA[5:0] = 13h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQS oscillator count – MSB Table 66: MR19 DQS Oscillator Count Function DQS oscillator count – MSB (WR training DQS oscillator) Type OP Read-only OP[7:0] Definition 0h–FFh MSB DRAM DQS oscillator count Notes: 1. MR19 reports the MSB bits of the DRAM DQS oscillator count. The DRAM DQS oscillator count value is used to train DQS to the DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically adjust the phase of DQS relative to DQ. 2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS oscillator count. 3. A new MPC[START DQS OSCILLATOR] should be issued to reset the contents of MR18/MR19. 4. Notes 1–3 apply to the entire table. Table 67: MR20 Register Information (MA[5:0] = 14h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Upper-byte invert register for DQ calibration Table 68: MR20 Register Information Function Upper-byte invert for DQ calibration Type OP Write-only OP[7:0] Definition The following values may be written for any operand OP[7:0] and will be applied to the corresponding DQ locations DQ[15:8] within a byte lane 0b: Do not invert 1b: Invert the DQ calibration patterns in MR32 and MR40 Default value for OP[7:0] = 55h Notes: 1. This register will invert the DQ calibration pattern found in MR32 and MR40 for any single DQ or any combination of DQ. For example, if MR20 OP[7:0] = 00010101b, the DQ calibration patterns transmitted on DQ[15, 14, 13, 11, 9] will not be inverted, but the DQ calibration patterns transmitted on DQ[12, 10, 8] will be inverted. 2. DM[1] is not inverted and always transmits the true data contained in MR32 and MR40. 3. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3 OP[6]. 4. Notes 1–3 apply to entire table. Table 69: MR20 Invert Register Pin Mapping Pin DQ8 DQ9 DQ10 DQ11 DMI1 DQ12 DQ13 DQ14 DQ15 MR20 OP0 OP1 OP2 OP3 No invert OP4 OP5 OP6 OP7 Table 70: MR21 Register Information (MA[5:0] = 15h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RFU CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 71: MR22 Register Information (MA[5:0] = 16h) OP7 OP6 ODTD for x8_2ch OP5 OP4 OP3 ODTD-CA ODTE-CS ODTE-CK OP2 OP1 OP0 SOC ODT Table 72: MR22 Register Information Function SOC ODT (controller ODT value for VOH calibration) Type OP Write-only OP[2:0] Data Notes 000b: Disable (default) 1, 2, 3 001b: RZQ/1 (Illegal if MR3 OP[0] = 0b) 010b: RZQ/2 011b: RZQ/3 (Illegal if MR3 OP[0] = 0b) 100b: RZQ/4 101b: RZQ/5 (Illegal if MR3 OP[0] = 0b) 110b: RZQ/6 (Illegal if MR3 OP[0] = 0b) 111b: RFU ODTE-CK (CK ODT enabled for non-terminating rank) Write-only OP[3] ODT bond PAD is ignored 2, 3 0b: ODT-CK enable (default) 1b: ODT-CK disable ODTE-CS (CS ODT enabled for non-terminating rank) Write-only OP[4] ODT bond PAD is ignored 2, 3 0b: ODT-CS enable (default) 1b: ODT-CS disable ODTD-CA (CA ODT termina- Write-only tion disable) OP[5] ODT bond PAD is ignored 2, 3 0b: CA ODT enable (default) 1b: CA ODT disable ODTD for x8_2ch (Byte) mode Write-only OP[7:6] See Byte Mode section Notes: 1. All values are typical. 2. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. Table 73: MR23 Register Information (MA[5:0] = 17h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQS interval timer run-time setting CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 74: MR23 Register Information Function Type OP DQS interval timer run-time Write-only OP[7:0] Data 00000000b: Disabled (default) 00000001b: DQS timer stops automatically at the 16th clock after timer start 00000010b: DQS timer stops automatically at the 32nd clock after timer start 00000011b: DQS timer stops automatically at the 48th clock after timer start 00000100b: DQS timer stops automatically at the 64th clock after timer start --------- Through --------00111111b: DQS timer stops automatically at the (63 × 16)th clock after timer start 01XXXXXXb: DQS timer stops automatically at the 2048th clock after timer start 10XXXXXXb: DQS timer stops automatically at the 4096th clock after timer start 11XXXXXXb: DQS timer stops automatically at the 8192nd clock after timer start Notes: 1. MPC command with OP[6:0] = 1001101b (STOP DQS INTERVAL OSCILLATOR) stops the DQS interval timer in the case of MR23 OP[7:0] = 00000000b. 2. MPC command with OP[6:0] = 1001101b (STOP DQS INTERVAL OSCILLATOR) is illegal with valid nonzero values in MR23 OP[7:0]. 3. Notes 1–2 apply to entire table. Table 75: MR24 Register Information (MA[5:0] = 18h) when MR0 OP[2] = 0b OP7 OP6 TRR mode OP5 OP4 OP3 TRR mode BAn OP2 Unlimited MAC OP1 OP0 MAC value Table 76: MR24 Register Information when MR0 OP[2] = 0b Function Type MAC value Read OP Data Notes OP[2:0] 000b: Unknown (OP[3] = 0) or unlimited (OP[3] = 1) 1 001b: 700K 010b: 600K 011b: 500K 100b: 400K 101b: 300K 110b: 200K 111b: Reserved CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 76: MR24 Register Information when MR0 OP[2] = 0b (Continued) Function Type OP Unlimited MAC Read OP[3] Data Notes 0b: OP[2:0] defines the MAC value 2 1b: Unlimited MAC value TRR mode BAn Write OP[6:4] 000b: Bank 0 001b: Bank 1 010b: Bank 2 011b: Bank 3 100b: Bank 4 101b: Bank 5 110b: Bank 6 111b: Bank 7 TRR mode Write OP[7] 0b: Disabled (default) 1b: Enabled Notes: 1. OP[2:0] = 000b Unknown means that the device is not tested for tMAC and pass/fail values are unknown. OP[2:0] = 000b Unlimited means that there is no restriction on the number of activates between refresh windows. However, specific attempts to by-pass TRR may result in data disturb. 2. When OP[3] = 1b, MR24 OP[2:0] set to 000b. Table 77: MR24 Register Information (MA[5:0] = 18h) when MR0 OP[2] = 1b OP7 OP6 OP5 OP4 OP3 RAAMMT RAAIMT OP2 OP1 OP0 RFM Table 78: MR24 Register Information when MR0 OP[2] = 1b Function Type OP RFM(RFM required) Read OP[0] Data Notes 0b: RFM not required 1 1b: RFM required RAAIMT (Rolling accumulated ACT initial management threshold) Read OP[5:1] 00000b: Invalid 1 00001b: 8 00010b: 16 ..... 11110b: 240 11111b: 248 RAAMMT (Rolling accumulated ACT maximum management threshold) Read OP[7:6] 00b: 2X 1 01b: 4X 10b: 6X 11b: 8X CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Note: 1. Vendor programmed. Table 79: MR25 Register Information (MA[5:0] = 19h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 Table 80: MR25 Register Information Function PPR resources Type OP Read-only OP[7:0] Data 0b: PPR resource is not available 1b: PPR resource is available Note: 1. When OP[n] = 0, there is no PPR resource available for that bank. When OP[n] = 1, there is a PPR resource available for that bank, and PPR can be initiated by the controller. Table 81: MR26:29 Register Information (MA[5:0] = 1Ah–1Dh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP2 OP1 OP0 Reserved for future use Table 82: MR30 Register Information (MA[5:0] = 1Eh) OP7 OP6 OP5 OP4 OP3 Valid 0 or 1 Table 83: MR30 Register Information Function SDRAM will ignore Type OP Write-only OP[7:0] Data Don't care Note: 1. This register is reserved for testing purposes. The logical data values written to OP[7:0] will have no effect on SDRAM operation; however, timings need to be observed as for any other MR access command. Table 84: MR31 Register Information (MA[5:0] = 1Fh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP2 OP1 OP0 Reserved for future use Table 85: MR32 Register Information (MA[5:0] = 20h) OP7 OP6 OP5 OP4 OP3 DQ calibration pattern A (default = 5Ah) CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 86: MR32 Register Information Feature Return DQ calibration pattern MR32 + MR40 Type OP Write-only OP[7:0] Data Notes Xb: An MPC command issued with OP[6:0] = 1000011b causes the device to return the DQ calibration pattern contained in this register and (followed by) the contents of MR40. A default pattern 5Ah is loaded at power-up or reset, or the pattern may be overwritten with a MRW to this register. The contents of MR15 and MR20 will invert the MR32/MR40 data pattern for a given DQ (see MR15/MR20 for more information). 1, 2, 3 Notes: 1. The patterns contained in MR32 and MR40 are transmitted on DQ[15:0] and DMI[1:0] when read DQ calibration is initiated via an MPC command. The pattern is transmitted serially on each data lane and organized little endian such that the low-order bit in a byte is transmitted first. If the data pattern is 27H, the first bit transmitted is a 1 followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111. 2. MR15 and MR20 may be used to invert the MR32/MR40 data pattern on the DQ pins. See MR15 and MR20 for more information. Data is never inverted on the DMI[1:0] pins. 3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3 OP[6]. 4. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3 OP[6]. Table 87: MR33:35 Register Information (MA[5:0] = 21h–23h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP3 OP2 OP1 OP0 Do not use Table 88: MR36 Register Information (MA[5:0] = 24h) OP7 OP6 OP5 OP4 RFU OP0 RAADEC Table 89: MR36 Register Information Feature Type OP RAADEC (RAA count multiplier per RFM command) Read OP[1:0] Data Notes 00b: x1 1 01b: x1.5 10b: x2 11b: RFU Note: 1. OP[1:0] RAADEC bits are valid only when MR0 OP[2] (RFM support) = 1. Table 90: MR37:38 Register Information (MA[5:0] = 25h–26h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP3 OP2 OP1 OP0 Do not use Table 91: MR39 Register Information (MA[5:0] = 27h) OP7 OP6 OP5 OP4 Valid 0 or 1 CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 92: MR39 Register Information Function SDRAM will ignore Type OP Data Write-only OP[7:0] Don't care Note: 1. This register is reserved for testing purposes. The logical data values written to OP[7:0] will have no effect on SDRAM operation; however, timings need to be observed as for any other MR access command. Table 93: MR40 Register Information (MA[5:0] = 28h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQ calibration pattern B (default = 3Ch) Table 94: MR40 Register Information Function Return DQ calibration pattern MR32 + MR40 Type OP Write-only OP[7:0] Data Notes Xb: A default pattern 3Ch is loaded at power-up or reset, or the pattern may be overwritten with a MRW to this register. See MR32 for more information. 1, 2, 3 Notes: 1. The pattern contained in MR40 is concatenated to the end of MR32 and transmitted on DQ[15:0] and DMI[1:0] when read DQ calibration is initiated via an MPC command. The pattern is transmitted serially on each data lane and organized little endian such that the low-order bit in a byte is transmitted first. If the data pattern in MR40 is 27H, the first bit transmitted will be a 1, followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111. 2. MR15 and MR20 may be used to invert the MR32/MR40 data patterns on the DQ pins. See MR15 and MR20 for more information. Data is never inverted on the DMI[1:0] pins. 3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3 OP[6]. 4. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3 OP[6]. Table 95: MR41:47 Register Information (MA[5:0] = 29h–2Fh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP2 OP1 OP0 Do not use Table 96: MR48:63 Register Information (MA[5:0] = 30h–3Fh) OP7 OP6 OP5 OP4 OP3 Reserved for future use Commands and Timing Commands transmitted on the CA bus are encoded into two parts and are latched on two consecutive rising edges of the clock. This is called 2-tick CA capture because each command requires two clock edges to latch and decode the entire command. Truth Tables Truth tables provide complementary information to the state diagram. They also clarify device behavior and applicable restrictions when considering the actual state of the banks. Unspecified operations and timings are illegal. To ensure proper operation after an illegal event, the device must be either reset by asserting the RESET_n command or powered down and then restarted using the specified initialization sequence before normal operation can continue. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification CKE signal has to be held HIGH when the commands listed in the command truth table input. Table 97: Command Truth Table SDR CA Pins Command CS CA0 CA1 CA2 CA3 CA4 CA5 MRW-1 H L H H L L OP7 1 L MA0 MA1 MA2 MA3 MA4 MA5 2 H L H H L H OP6 1 L OP0 OP1 OP2 OP3 OP4 OP5 2 H L H H H L V 1 L MA0 MA1 MA2 MA3 MA4 MA5 2 H L L L H L AB 1 L BA0 BA1 BA2 RFM V V 2 H L L L H H V 1 MRW-2 MRR-1 REFRESH (all/per bank) ENTER SELF REFRESH ACTIVATE-1 ACTIVATE-2 WRITE-1 EXIT SELF REFRESH MASK WRITE-1 RFU L V H L R12 R13 R14 R15 1 L BA0 BA1 BA2 R16 R10 R11 2 H R17 R18 R6 R7 R8 R9 1 L R0 R1 R2 R3 R4 R5 2 H L L H L L BL 1 L BA0 BA1 BA2 V C9 AP 2 H L L H L H V 1 L V L L H H L BL 1 L BA0 BA1 BA2 V C9 AP 2 H L L H H H V 1 H L V H H V V L H L L RFU H H L L READ-1 2 V 2 1, 2, 3, 4, 14, 15 1, 2 1, 2, 3, 10 1, 10, 13 1, 2, 3, 6, 7, 9 1, 2 1, 2, 3, 5, 6, 7, 9 1, 2 1, 2 1, 2 2 L H L L L BL 1 L BA0 BA1 BA2 V C9 AP 2 75 1, 2, 12 2 H CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 1, 11 2 V L 1, 11 2 H H Notes 2 H L RFU CK Edge 1, 2, 3, 6, 7, 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 97: Command Truth Table (Continued) SDR CA Pins Command CS CA0 CA1 CA2 CA3 CA4 CA5 CAS-2 (WRITE-2, MASKED WRITE-2, READ-2, MRR-2, MPC (except NOP) H L H L L H C8 1 L C2 C3 C4 C5 C6 C7 2 PRECHARGE (all/per bank) H L L L L H AB 1 L BA0 BA1 BA2 V V V 2 MPC (TRAIN, NOP) H L L L L L OP6 1 L OP0 OP1 OP2 OP3 OP4 OP5 2 DESELECT L X CK Edge 1 Notes 1, 8, 9 1, 2, 3, 4 1, 9 1, 2 Notes: 1. All commands except for DESELECT are two clock cycles and are defined by the current state of CS and CA[5:0] at the rising edge of the clock. DESELECT command is one clock cycle and is not latched by the device. 2. V = H or L (a defined logic level); X = "Don't Care," in which case CS, CK_t, CK_c, and CA[5:0] can be floated. 3. Bank addresses BA[2:0] determine which bank is to be operated upon. 4. AB HIGH during PRECHARGE or REFRESH commands indicate the command must be applied to all banks, and the bank addresses are "Don't Care." 5. MASK WRITE-1 command only supports BL16. For MASK WRITE-1 commands, CA5 must be driven LOW on the first rising clock cycle (R1). 6. AP HIGH during a WRITE-1, MASK WRITE-1, or READ-1 command indicates that an auto precharge will occur to the bank the command is operating on. AP LOW indicates that no auto precharge will occur and the bank will remain open upon completion of the command. 7. When enabled in the mode register, BL HIGH during a WRITE-1, MASK-WRITE-1, or READ-1 command indicates the burst length should be set on-the-fly to BL = 32; BL LOW during one of these commands indicates the burst length should be set on-the-fly to BL = 16. If on-the-fly burst length is not enabled in the mode register, this bit should be driven to a valid level and is ignored by the device. 8. For CAS-2 commands (WRITE-2, MASK WRITE-2, READ-2, MRR-2, or MPC (only WRITE-FIFO, READ-FIFO, and READ DQ CALIBRATION)), C[1:0] are not transmitted on the CA [5:0] bus and are assumed to be zero. Note that for CAS-2 WRITE-2 or CAS-2 MASK WRITE-2 command, C[3:2] must be driven LOW. 9. WRITE-1, MASK-WRITE-1, READ-1, MODE REGISTER READ-1, or MPC (only WRITE-FIFO, READ-FIFO, and READ DQ CALIBRATION) command must be immediately followed by CAS-2 command consecutively without any other command in between. WRITE-1, MASK WRITE-1, READ-1, MRR-1, or MPC (only WRITE-FIFO, READ-FIFO, and READ DQ CALIBRATION) command must be issued first before issuing CAS-2 command. MPC (only START and STOP DQS OSCILLATOR, ZQCAL START and LATCH) commands do not require CAS-2 command; they require two additional DES or NOP commands consecutively before issuing any other commands. 10. The ACTIVATE-1 command must be followed by the ACTIVATE-2 command consecutively without any other command between them. The ACTIVATE-1 command must be issued prior to the ACTIVATE-2 command. When the ACTIVATE-1 command is issued, the ACTIVATE-2 command must be issued before issuing another ACTIVATE-1 command. 11. The MRW-1 command must be followed by the MRW-2 command consecutively without any other command between them. The MRW-1 command must be issued prior to the MRW-2 command. 12. The MRR-1 command must be followed by the CAS-2 command consecutively without any other commands between them. The MRR-1 command must be issued prior to the CAS-2 command. 13. For device densities not requiring R17 and R18, R17 and R18 must both be driven High for every ACT-2 command to maintain backward compatibility. 14. CA3 R2 edge is V when RFM is not required, but becomes RFM when read-only MR24 OP[0] = 1b. 15. Issuing the RFMpb or RFMab command allows the device to use the command period for additional refresh management. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification 16. Commands are transmitted to the device across a six-lane interface and use CK, CKE, and CS to control the capture of transmitted data. This is applies to entire table. ACTIVATE Command The ACTIVATE command must be executed before a READ or WRITE command can be issued. The ACTIVATE command is issued in two parts: The bank and upper-row addresses are entered with activate-1 and the lower-row addresses are entered with ACTIVATE-2. ACTIVATE-1 and ACTIVATE-2 are executed by strobing CS HIGH while setting CA[5:0] at valid levels (see Command table) at the rising edge of CK. The bank addresses (BA[2:0]) are used to select the desired bank. The row addresses (R[15:0]) are used to determine which row to activate in the selected bank. The ACTIVATE-2 command must be applied before any READ or WRITE operation can be executed. The device can accept a READ or WRITE command at time tRCD after the ACTIVATE-2 command is sent. After a bank has been activated, it must be precharged to close the active row before another ACTIVATE-2 command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive ACTIVATE-2 commands to the same bank is determined by the row cycle time of the device (tRC). The minimum time interval between ACTIVATE-2 commands to different banks is tRRD. Certain restrictions must be observed for bank ACTIVATE and REFpb operations. • Four-activate window (tFAW): No more than 4 banks may be activated (or refreshed, in the case of REFpb) per channel in a rolling tFAW window. Convert to clocks by dividing tFAW[ns] by tCK[ns] and rounding up to the next integer value. As an example of the rolling window, if RU[(tFAW/tCK)] is 64 clocks, and an ACTIVATE command is issued on clock N, no more than three additional ACTIVATE commands may be issued between clock N + 1 and N + 63. REFpb also counts as bank activation for the purposes of tFAW. • 8-bank per channel, precharge all banks (AB) allowance: tRP for a PRECHARGE ALL BANKS command for an 8-bank device must equal tRPab, which is greater than tRPpb. Figure 16: ACTIVATE Command T0 T1 T2 T3 Ta0 RA RA BA0 RA RA RA Ta1 Ta2 Ta3 RA RA Tb0 Tb1 Tb2 Tb3 Valid BA0 CA CA Tc0 Tc1 Td0 Td1 Td2 Td3 RA RA Td4 Td5 CK_c CK_t CKE CS CA RA BA1 Valid RA BA0 RA BA0 tRP tRRD tRCD Command ACTIVATE-1 ACTIVATE-2 DES ACTIVATE-1 ACTIVATE-2 READ1 DES CAS2 DES PRECHARGE per bank DES ACTIVATE-1 ACTIVATE-2 DES DES tRAS tRC Don’t Care Note: 1. A PRECHARGE command uses tRPab timing for all-bank precharge and tRPpb timing for single-bank precharge. In this figure, tRP is used to denote either all-bank precharge or a single-bank precharge. tCCD = MIN, 1.5nCK postamble, 533 MHz < clock frequency ≤ 800 MHz, ODT worst timing case. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 17: tFAW Timing T0 T1 T2 T3 Ta0 RA RA BA0 RA RA RA Ta1 Ta2 Ta3 RA RA Tb0 Tb1 Tb2 Tb3 RA BA2 RA RA Tc0 Tc1 Tc2 Tc3 RA RA Tc4 Td0 Td1 Td2 Td3 Td4 RA RA BA4 RA RA CK_c CK_t CKE CS CA Command ACTIVATE-1 ACTIVATE-2 DES RA BA1 ACTIVATE-1 ACTIVATE-2 tRRD RA DES ACTIVATE-1 ACTIVATE-2 RA DES RA BA3 ACTIVATE-1 ACTIVATE-2 DES DES ACTIVATE-1 ACTIVATE-2 tRRD tRRD t FAW Don’t Care Note: 1. REFpb may be substituted for one of the ACTIVATE commands for the purposes of tFAW. Read and Write Access Modes After a bank has been activated, a READ or WRITE command can be executed. This is accomplished by asserting CKE asynchronously, with CS and CA[5:0] set to the proper state (see Command Truth Table) on the rising edge of CK. The device provides a fast column access operation. A single READ or WRITE command will initiate a burst READ or WRITE operation, where data is transferred to/from the device on successive clock cycles. Burst interrupts are not allowed; however, the optimal burst length may be set on-the-fly (see Command Truth Table). Preamble and Postamble The DQS strobe for the device requires a preamble prior to the first latching edge (the rising edge of DQS_t with data valid), and it requires a postamble after the last latching edge. The preamble and postamble options are set via MODE REGISTER WRITE commands. The read preamble is two tCK in length and is either static or has one clock toggle before the first latching edge. The read preamble option is enabled via MRW to MR1 OP[3] (0 = Static; 1 = Toggle). The read postamble has a programmable option to extend the postamble by 1nCK (tRPSTE). The extended postamble option is enabled via MRW to MR1 OP[7] (0 = 0.5nCK; 1 = 1.5nCK). CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 78 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 18: DQS Read Preamble and Postamble – Toggling Preamble and 0.5nCK Postamble T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command RD-1 CAS-2 tDQSCK RL tRPRE DQS_c DQS_t tRPST tDQSQ DQ DMI DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 n15 Notes: 1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK. 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don’t Care" prior to the start of tRPRE. No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tRPRE. Figure 19: DQS Read Preamble and Postamble – Static Preamble and 1.5nCK Postamble T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command RD-1 CAS-2 RL tDQSCK tRPRE DQS_c DQS_t tDQSQ DQ DMI tRPSTE DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 n15 Notes: 1. BL = 16, Preamble = Static, Postamble = 1.5nCK (extended). 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don’t Care" prior to the start of tRPRE. No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tRPRE. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 79 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 20: DQS Write Preamble and Postamble – 0.5nCK Postamble T0 T1 T2 T3 Valid Valid Valid Valid T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CKE CS CA Command WRITE-1 CAS-2 WL tDQSS t WPRE t WPST DQS_c DQS_t BL/2 tDQS2DQ DQ DMI DIN n0 DIN n1 DIN n2 DIN n3 DIN n8 DIN n9 DIN n10 DIN n11 DIN n12 DIN n13 DIN n14 DIN n15 Don’t Care Notes: 1. BL = 16, Postamble = 0.5nCK. 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don’t Care" prior to the start of tWPRE. No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tWPRE. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 80 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 21: DQS Write Preamble and Postamble – 1.5nCK Postamble T0 T1 T2 T3 Valid Valid Valid Valid T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CKE CS CA Command WRITE-1 CAS-2 WL tDQSS t t WPST WPRE DQS_c DQS_t BL/2 tDQS2DQ DQ DMI DIN n0 DIN n1 DIN n2 DIN n3 DIN n8 DIN n9 DIN n10 DIN n11 DIN n12 DIN n13 DIN n14 DIN n15 Don’t Care Notes: 1. BL = 16, Postamble = 1.5nCK. 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don’t Care" prior to the start of tWPRE. No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tWPRE. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 81 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Burst READ Operation A burst READ command is initiated with CKE, CS, and CA[5:0] asserted to the proper state on the rising edge of CK, as defined by the Command Truth Table. The command address bus inputs determine the starting column address for the burst. The two low-order address bits are not transmitted on the CA bus and are implied to be 0; therefore, the starting burst address is always a multiple of four (that is, 0x0, 0x4, 0x8, 0xC). The READ latency (RL) is defined from the last rising edge of the clock that completes a READ command (for example, the second rising edge of the CAS-2 command) to the rising edge of the clock from which the tDQSCK delay is measured. The first valid data is available RL × tCK + tDQSCK + tDQSQ after the rising edge of clock that completes a READ command. The data strobe output is driven tRPRE before the first valid rising strobe edge. The first data bit of the burst is synchronized with the first valid (post-preamble) rising edge of the data strobe. Each subsequent data-out appears on each DQ pin, edge-aligned with the data strobe. At the end of a burst, the DQS signals are driven for another half cycle postamble, or for a 1.5-cycle postamble if the programmable postamble bit is set in the mode register. The RL is programmed in the mode registers. Pin timings for the data strobe are measured relative to the cross-point of DQS_t and DQS_c. Figure 22: Burst Read Timing T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T5 T6 T7 T15 T16 T17 T18 T19 BL BA0, CA, AP CAm CAm T20 T21 T22 T23 DES DES DES T33 T34 T35 T36 DES DES DES T41 T42 T43 T44 DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES DES t DES DES READ-1 CAS-2 DES CCD = 16 RL = 14 RL = 14 t DQSCK DES t DQSCK BL/2 = 8 BL/2 = 16 t t RPST RPRE DQS_c DQS_t tDQSQ tDQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n7 n26 n27 n28 n29 n30 n31 m0 m1 m10 m11 m12 m13 m14 m15 n1 n2 n6 n0 n3 n4 n5 DQ DMI Don’t Care Notes: 1. BL = 32 for column n, BL = 16 for column m, RL = 14, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 23: Burst Read Followed by Burst Write or Burst Mask Write T0 T1 T2 T3 BL BA0, CA, AP CA CA T4 T5 Ta0 Ta1 Ta2 BL BA0, CA, AP Ta3 Ta4 CA CA Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 DES DES DES DES DES DES Tb6 Tb7 Tc0 Tc1 DES DES DES DES Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 DES DES CK_c CK_t CS CA READ-1 Command CAS-2 DES WR-1/MWR-1 DES DES CAS-2 RL + RU( tDQSCK(MAX)/ tCK) + BL/2 + RD( tRPST) - WL + tWPRE WL t DQSCK RL t DES DES DES DES t DQSS BL/2 = 8 t RPRE WPRE DQS_c DQS_t tDQSQ DQ DMI tDQS2DQ tRPST DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n9 n10 n11 n12 n13 n14 n15 DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n9 n10 n11 n12 n13 n14 n15 n0 Don’t Care Notes: 1. BL = 16, Read preamble = Toggle, Read postamble = 0.5nCK, Write preamble = 2nCK, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DOUT n = data-out from column n and DIN n = data-in to column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 24: Seamless Burst Read T0 T1 T2 T3 Ta0 Ta1 Ta2 BL BA0, CA, AP CAn CAn BL BA0, CA, AP Ta3 Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 DES DES DES Tc2 Tc3 Td0 Td1 Td2 Td3 Te0 Te1 DES DES DES DES DES Te2 Te3 CK_c CK_t CS CA Command READ-1 CAS-2 DES CAm CAm CAS-2 READ-1 BL DES BA1, CA, AP CAn READ-1 CAn CAS-2 DES DES DES DES t DQSCK RL t DQSCK RL RL DES t DQSCK t RPRE DQS_c DQS_t tDQSQ DQ DMI tDQSQ tDQSQ tRPST DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n15 n10 n11 n12 n13 n14 n0 n1 n10 n11 n12 n13 n14 n15 m0 m1 m10 m11 m12 m13 m14 m15 n0 n1 Bank 0 Bank 1 Don’t Care Notes: 1. BL = 16, tCCD = 8, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 83 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Read Timing Figure 25: Read Timing T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc0 Tc1 Tc2 Tc3 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command RD-1 CAS-2 t HZ(DQS) t RL DQSCK t LZ(DQS) t RPRE DQS_c DQS_t t DQSQ t RPST t HZ(DQ) t LZ(DQ) DQ DMI DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 n15 Notes: 1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK. 2. DQS, DQ, and DMI terminated VSSQ. 3. Output driver does not turn on before an endpoint of tLZ(DQS) and tLZ(DQ). 4. Output driver does not turn off before an endpoint of tHZ(DQS) and tHZ(DQ). CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 84 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ). This section shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single ended. tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) Figure 26: tLZ(DQS) Method for Calculating Transitions and Endpoint CK_t – CK_c crossing at the second CAS-2 of READ command CK_t CK_c tLZ(DQS) DQS_c VOH VSW2 0.5 x VOH VSW1 End point: Extrapolated point 0V Notes: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5. 2. Termination condition for DQS_t and DQS_C = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 85 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 27: tHZ(DQS) Method for Calculating Transitions and Endpoint CK_t – CK_c crossing at the second CAS-2 of READ command CK_t CK_c tHZ(DQS) End point: Extrapolated point VOH VSW2 0.5 x VOH VSW1 DQS_c 0V Notes: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5. 2. Termination condition for DQS_t and DQS_C = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements. Table 98: Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements Measured Parameter Measured Parameter Symbol DQS_c Low-Z time from CK_t, CK_c tLZ(DQS) DQS_c High-Z time from CK_t, CK_c t CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN Vsw1 Vsw2 Unit 0.4 × VOH 0.6 × VOH V 0.4 × VOH HZ(DQS) 86 0.6 × VOH Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) Figure 28: tLZ(DQ) Method for Calculating Transitions and Endpoint CK_t – CK_c crossing at the second CAS-2 of READ command CK_t CK_c t LZ(DQ) DQs VOH VSW2 0.5 x VOH VSW1 End point: Extrapolated point 0V Notes: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5. 2. Termination condition for DQ and DMI = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements. Figure 29: tHZ(DQ) Method for Calculating Transitions and Endpoint CK_t – CK_c crossing at the second CAS-2 of READ command CK_t CK_c tHZ(DQ) End point: Extrapolated point VOH VSW2 0.5 x VOH VSW1 DQs 0V Notes: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5. 2. Termination condition for DQ and DMI = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 99: Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements Measured Parameter Measured Parameter Symbol DQ Low-Z time from CK_t, CK_c tLZ(DQ) DQ High-Z time from CK_t, CK_c t Vsw1 Vsw2 Unit 0.4 × VOH 0.6 × VOH V 0.4 × VOH HZ(DQ) 0.6 × VOH Burst WRITE Operation A burst WRITE command is initiated with CKE, CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by the Command Truth Table. Column addresses C[3:2] should be driven LOW for burst WRITE commands, and column addresses C[1:0] are not transmitted on the CA bus and are assumed to be zero so that the starting column burst address is always aligned with a 32-byte boundary. The WRITE latency (WL) is defined from the last rising edge of the clock that completes a WRITE command (for example, the second rising edge of the CAS-2 command) to the rising edge of the clock from which tDQSS is measured. The first valid latching edge of DQS must be driven WL × t CK + tDQSS after the rising edge of clock that completes a WRITE command. The device uses an unmatched DQS DQ path for lower power, so the DQS strobe must arrive at the SDRAM ball prior to the DQ signal by tDQS2DQ. The DQS strobe output must be driven tWPRE before the first valid rising strobe edge. The tWPRE preamble is required to be 2 × tCK at any speed ranges. The DQS strobe must be trained to arrive at the DQ pad latch center-aligned with the DQ data. The DQ data must be held for TdiVW, and the DQS must be periodically trained to stay roughly centered in the TdiVW. Burst data is captured by the SDRAM on successive edges of DQS until the 16- or 32-bit data burst is complete. The DQS strobe must remain active (toggling) for tWPST (write postamble) after the completion of the burst WRITE. After a burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the same bank can be issued. Signal input timings are measured relative to the cross point of DQS_t and DQS_c. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 88 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 30: Burst WRITE Operation T0 T1 T2 T3 BL BA0, CA, AP CA CA T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Valid BA0 Tc3 Tc4 Td0 Td1 Td2 Td3 Tb4 Td5 RA BA0, RA RA RA CK_c CK_t CS CA Command CAS-2 WRITE-1 DES DES DES DES DES WL DES DES DES DES DES DES DES BL/2 + 1 Clock tDQSS tWPRE DES PRECHARGE DES DES DES tWR DES ACT-2 ACT-1 tRP (MIN) tDSH tDSS DQS_c tWPST DQS_t tDQS2DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n5 n12 n13 n14 n15 DQ tDQSS (Nominal) tWPRE DQS_c DQS_t tDQS2DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n11 n12 n13 n14 n15 tDQSS (MAX) DQ tWPRE DQS_c DQS_t tDQS2DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n11 n12 n13 n14 n15 DQ Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DIN n = data-in to column n. 3. tWR starts at the rising edge of CK after the last latching edge of DQS. 4. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 31: Burst Write Followed by Burst Read T0 T1 T2 T3 BL BA0, CA, AP CA CA T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 BL BA0, CA, AP CA CA Tc7 Tc8 Tc9 Tc10 DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES DES DES DES DES WL DES DES DES DES DES DES DES tWPRE DES DES tWTR BL/2 + 1 Clock tDQSS DES READ-1 CAS-2 RL (MIN) tDSH tDSS tWPST DQS_c DQS_t DQ tDQS2DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n5 n12 n13 n14 n15 Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification 2. DIN n = data-in to column n. 3. The minimum number of clock cycles from the burst WRITE command to the burst READ command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)]. 4. tWTR starts at the rising edge of CK after the last latching edge of DQS. 5. DES commands are shown for ease of illustration; other commands may be valid at these times. Write Timing Figure 32: Write Timing T0 T1 T2 T3 BL BA0, CA, AP CA CA T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 DES DES DES DES DES DES DES DES Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 DES DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES WL tDQSS tDQSS (MIN) tWPRE (MIN) tDSH tDSS tWPST DQS_c DQS_t tDQS2DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n5 n12 n13 n14 n15 DQ tDQSS tDQSS (Nominal) (Nominal) tDSH tWPRE tDSS DQS_c DQS_t tDQS2DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n11 n12 n13 n14 n15 DQ tDQSS tDQSS (MAX) (MAX) tWPRE tDSH tDSS DQS_c DQS_t tDQS2DQ tDQSH tDQSL DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n11 n12 n13 n14 n15 DQ Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK. 2. DIN n = data-in to column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification tWPRE Calculation for ATE (Automatic Test Equipment) Figure 33: Method for Calculating tWPRE Transitions and Endpoints CK_t Vref(CA) CK_c Resulting differential signal relevant for tWPRE specification Vsw2 Vsw1 DQS_t - DQS_c 0V Begin point: Extrapolated point tWPRE Note: 1. Termination condition for DQS_t, DQS_c, DQ, and DMI = 50 ohms to VSSQ. Table 100: Method for Calculating tWPRE Transitions and Endpoints Measured Parameter DQS_t, DQS_c differential write preamble CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN Measured Parameter Symbol t WPRE 91 Vsw1 Vsw2 Unit VIHL_AC × 0.3 VIHL_AC × 0.7 V Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification tWPST Calculation for ATE (Automatic Test Equipment) Figure 34: Method for Calculating tWPST Transitions and Endpoints CK_t Vref(CA) CK_c Resulting differential signal relevant for tWPST specification 0V Vsw2 Vsw1 DQS_t - DQS_c End point: Extrapolated point tWPST Notes: 1. Termination condition for DQS_t, DQS_c, DQ, and DMI = 50 ohms to VSSQ. 2. Write postamble: 0.5tCK 3. The method for calculating differential pulse widths for 1.5tCK postamble is same as 0.5tCK postamble. Table 101: Reference Voltage for tWPST Timing Measurements Measured Parameter DQS_t, DQS_c differential write postamble Measured Parameter Symbol tWPST Vsw1 Vsw2 Unit –(VIHL_AC × 0.7) –(VIHL_AC × 0.3) V MASK WRITE Operation The device requires that WRITE operations that include a byte mask anywhere in the burst sequence must use the MASK WRITE command. This allows the device to implement efficient data protection schemes based on larger data blocks. The MASK WRITE-1 command is used to begin the operation, followed by a CAS-2 command. A MASKED WRITE command to the same bank cannot be issued until t CCDMW later, to allow the device to finish the internal READ-MODIFY-WRITE operation. One data-mask-invert (DMI) pin is provided per byte lane, and the data-mask-invert timings match data bit (DQ) timing. See Data Mask Invert for more information on the use of the DMI signal. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 35: MASK WRITE Command – Same Bank T0 T1 T2 T3 BL BA0, CA, AP CA CA T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 BL BA0, CA, AP Tc5 Tc6 CA CA Tc7 Tc8 Tc9 Tc10 DES DES DES DES CK_c CK_t CS CA Command MASK WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES MASK WRITE-1 CAS-2 tCCDMW WL WL tDQSS(MIN) t tWPRE WPST DQS_c DQS_t tDQS2DQ DIN n0 DQ DMI DIN DIN n1 n2 DIN DIN n3 n4 DIN DIN DIN DIN n5 n12 n13 n14 DIN n15 Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DIN n = data-in to column n. 3. Mask-write supports only BL16 operations. For BL32 configuration, the system needs to insert only 16-bit wide data for MASKED WRITE operation. 4. DES commands are shown for ease of illustration; other commands may be valid at these time. Figure 36: MASK WRITE Command – Different Bank T0 T1 T2 T3 T8 T9 BL BA0, CA, AP CA CA BL BA1, CA, AP T10 T11 CA CA T16 T17 T18 T19 T24 T25 T26 T27 T32 T33 T34 T35 BL BA2, CA, AP CA CA BL BA3, CA, AP CA CA BL BA0, CA, AP CA CA T36 T37 T38 DES DES DES CK_c CK_t CS CA Command MASK WRITE-1 CAS-2 MASK WRITE-1 DES CAS-2 DES MASK WRITE-1 tCCD DES CAS-2 MASK WRITE-1 tCCD DES CAS-2 tCCD MASK WRITE-1 CAS-2 tCCD tCCDMW WL tDQSS tWPRE DQS_c DQS_t tDQS2DQ DQ DMI DIN n0 DIN n1 DIN n2 DIN DIN n3 n10 DIN DIN DIN DIN DIN n11 n12 n13 n14 n15 DIN n0 DIN DIN n1 n2 DIN DIN n3 n10 DIN DIN n11 n12 DIN DIN DIN n13 n14 n15 DIN n0 DIN n1 DIN DIN n2 n10 DIN DIN n11 n12 DIN DIN DIN n13 n14 n15 DIN n0 DIN n1 DIN n2 DIN DIN n3 n4 DIN n5 DIN n6 DIN DIN n8 n7 Don’t Care Notes: 1. BL = 16, DQ/DQS/DMI: VSSQ termination. 2. DIN n = data-in to column n. 3. Mask-write supports only BL16 operations. For BL32 configuration, the system needs to insert only 16-bit wide data for MASKED WRITE operation. 4. DES commands are shown for ease of illustration; other commands may be valid at these time. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Mask Write Timing Constraints for BL16 Table 102: Same Bank (ODT Disabled) Next CMD Current CMD ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE ACTIVE Illegal RU(tRCD/tCK) RU(tRCD/tCK) RU(tRCD/tCK) RU(tRAS/tCK) READ (with BL = 16) Illegal 81 RL + BL/2 + RL + RU(tDQSCK(MAX)/t RU(tDQSCK(MAX)/t MAX{(8,RU(tRTP/tC K)} - 8 CK) + BL/2 - WL + CK) + BL/2 - WL + tWPRE + RD(tRPST) tWPRE + RD(tRPST) READ (with BL = 32) Illegal 162 RL + BL/2 + RL + RU(tDQSCK(MAX)/t RU(tDQSCK(MAX)/t MAX{(8,RU(tRTP/tC K)} - 8 CK) + BL/2 - WL + CK) + BL/2 - WL + tWPRE + RD(tRPST) tWPRE + RD(tRPST) WRITE (with BL = 16) Illegal WL + 1+ BL/2 + RU(tWTR/tCK) 81 WRITE (with BL = 32) Illegal WL + 1 + BL/2 + RU(tWTR/tCK) 162 MASK WRITE Illegal WL + 1 + BL/2 + RU(tWTR/tCK) PRECHARGE RU(tRP/tCK), RU(tRPab/tCK) Illegal CCDMW3 WL + 1 + BL/2 + RU(tWR/tCK) CCDMW + 84 WL + 1 + BL/2 + RU(tWR/tCK) tCCD tCCDMW3 WL + 1 + BL/2 + RU(tWR/tCK) Illegal Illegal 4 t t Notes: 1. In the case of BL = 16, tCCD is 8 × tCK. 2. In the case of BL = 32, tCCD is 16 × tCK. 3. tCCDMW = 32 × tCK (4 × tCCD at BL = 16). 4. WRITE with BL = 32 operation is 8 × tCK longer than BL = 16. Table 103: Different Bank (ODT Disabled) Next CMD Current CMD ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE RU(tRRD/tCK) 4 4 4 22 READ (with BL = 16) 4 81 READ (with BL = 32) 4 162 WRITE (with BL = 16) 4 WL + 1+ BL/2 + RU(tWTR/tCK) 81 81 22 WRITE (with BL = 32) 4 WL + 1 + BL/2 + RU(tWTR/tCK) 162 162 22 ACTIVE RL + RL + RU(tDQSCK(MAX)/t RU(tDQSCK(MAX)/t CK) + BL/2 - WL + CK) + BL/2 - WL + t WPRE + RD(tRPST) tWPRE + RD(tRPST) RL + tDQSCK(MAX)/t RL + tDQSCK(MAX)/t 22 22 RU( RU( CK) + BL/2 - WL + CK) + BL/2 - WL + t t t WPRE + RD( RPST) WPRE + RD(tRPST) CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 94 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 103: Different Bank (ODT Disabled) (Continued) Next CMD Current CMD ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE 4 WL + 1 + BL/2 + RU(tWTR/tCK) 8 PRECHARGE 4 4 READ (BL = 16 or 32) MASK WRITE 1 PRECHARGE 1 22 4 4 4 WRITE (BL = 16 or 32) MASK WRITE PRECHARGE RU(tRCD/tCK) RU(tRCD/tCK) RU(tRAS/tCK) RL + BL/2 + MAX{(8,RU(tRTP/tC K)} - 8 8 Notes: 1. In the case of BL = 16, tCCD is 8 × tCK 2. In the case of BL = 32, tCCD is 16 × tCK Table 104: Same Bank (ODT Enabled) Next CMD Current CMD ACTIVE ACTIVE Illegal READ (with BL = 16) Illegal READ (with BL = 32) tRCD/tCK) RU( RL + 81 tDQSCK(MAX)/t RU( CK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) Illegal RU(tDQSCK(MAX)/t CK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) RL + RL + 162 tDQSCK(MAX)/t RU( CK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) WRITE (with BL = 16) Illegal WL + 1+ BL/2 + RU(tWTR/tCK) 81 WRITE (with BL = 32) Illegal WL + 1 + BL/2 + RU(tWTR/tCK) 162 MASK WRITE Illegal WL + 1 + BL/2 + RU(tWTR/tCK) PRECHARGE RU(tRP/tCK), RU(tRPab/tCK) Illegal t CCD Illegal RU(tDQSCK(MAX)/t CK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) tCCDMW3 tCCDMW + 84 BL/2 + MAX{(8,RU(tRTP/tC K)} - 8 WL + 1 + BL/2 + RU(tWR/tCK) WL + 1 + BL/2 + RU(tWR/tCK) CCDMW3 WL + 1 + BL/2 + RU(tWR/tCK) Illegal 4 t Notes: 1. In the case of BL = 16, tCCD is 8 × tCK. 2. In the case of BL = 32, tCCD is 16 × tCK. 3. tCCDMW = 32 × tCK (4 × tCCD at BL = 16). 4. WRITE with BL = 32 operation is 8 × tCK longer than BL = 16. Table 105: Different Bank (ODT Enabled) Next CMD Current CMD ACTIVE ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE RU(tRRD/tCK) 4 4 4 22 CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 105: Different Bank (ODT Enabled) (Continued) Next CMD Current CMD ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE 8 RL + RL + tDQSCK(MAX)/t RU(tDQSCK(MAX)/t RU( CK) + BL/2 + CK) + BL/2 + tRPST) - ODTRD( RD(tRPST) - ODTt Lon - RD( ODLon - RD(tODTon(MIN)/tCK) Ton(MIN)/tCK) 22 162 RL + RL + t RU(t DQSCK(MAX)/t RU( DQSCK(MAX)/ CK) + BL/2 + CK) + BL/2 + RD(tRPST) - ODTRD(tRPST) - ODTLon - RD(tODLon - RD(tODTon(MIN)/tCK) Ton(MIN)/tCK) 22 READ (with BL = 16) 4 READ (with BL = 32) 4 WRITE (with BL = 16) 4 WL + 1+ BL/2 + RU(tWTR/tCK) 81 81 22 WRITE (with BL = 32) 4 WL + 1 + BL/2 + RU(tWTR/tCK) 162 162 22 MASK WRITE 4 WL + 1 + BL/2 + RU(tWTR/tCK) 81 81 22 PRECHARGE 4 4 4 4 4 1 t Notes: 1. In the case of BL = 16, tCCD is 8 × tCK. 2. In the case of BL = 32, tCCD is 16 × tCK. Data Mask and Data Bus Inversion (DBI [DC]) Function Data mask (DM) is supported for WRITE operations and the data bus inversion DBI (DC) is supported for READ, WRITE, MASK WRITE, MRR, and MRW operations. DM and DBI (DC) functions are supported with byte granularity. DBI (DC) for READ operations (READ, MRR) can be enabled or disabled via MR3 OP[6]. DBI (DC) for WRITE operations (WRITE, MASK WRITE, MRW) can be enabled or disabled via MR3 OP[7]. DM for MASK WRITE operations can be enabled or disabled via MR13 OP[5]. The device has one data mask inversion (DMI) pin per byte and a total of two DMI pins per channel. The DMI signal is a bidirectional DDR signal, is sampled with the DQ signals, and is electrically identical to a DQ signal. There are eight possible states for the device with the DM and DBI (DC) functions. Table 106: Function Behavior of DMI Signal During WRITE, MASKED WRITE, and READ Operations DMI Signal DM Function Write DBI (DC) Read DBI (DC) During WRITE During MASKED WRITE During READ During MPC[WRIT E-FIFO] Disabled Disabled Disabled Don't Care1 Illegal1, 3 High-Z2 Don't Care1 High-Z2 High-Z2 Disabled Enabled Disabled DBI (DC)4 Illegal3 High-Z2 Train9 Train10 Train11 Disabled Disabled Enabled Don't Care1 Illegal3 DBI (DC)5 Train9 Train10 Train11 CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 96 During During MPC[READ MPC[READ -FIFO] DQ CAL] Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Table 106: Function Behavior of DMI Signal During WRITE, MASKED WRITE, and READ Operations DMI Signal DM Function Write DBI (DC) Read DBI (DC) During WRITE During MASKED WRITE During READ During MPC[WRIT E-FIFO] During During MPC[READ MPC[READ -FIFO] DQ CAL] Disabled Enabled Enabled DBI (DC)4 Illegal3 DBI (DC)5 Train9 Train10 Train11 Enabled Disabled Disabled Don't Care6 DM7 High-Z2 Train9 Train10 Train11 Enabled Enabled Disabled DBI (DC)4 DBI (DC)8 High-Z2 Train9 Train10 Train11 Enabled Disabled Enabled Don't Care6 DM7 DBI (DC)5 Train9 Train10 Train11 Enabled Enabled Enabled DBI (DC)4 DBI (DC)8 DBI (DC)5 Train9 Train10 Train11 Notes: 1. 2. 3. 4. The DMI input signal is "Don’t Care." DMI input receivers are turned off. DMI output drivers are turned off. The MASK WRITE command is not allowed and is considered an illegal command when the DM function is disabled. The DMI signal is treated as DBI and indicates whether the device needs to invert the write data received on DQ within a byte. The device inverts write data received on the DQ inputs if DMI is sampled HIGH and leaves the write data non-inverted if DMI is sampled LOW. 5. The device inverts read data on its DQ outputs associated within a byte and drives the DMI signal HIGH when more than four data bits = 1 within a given byte lane; otherwise, the device does not invert the read data and drives DMI signal LOW. 6. The device does not perform a MASK operation when it receives a WRITE (or MRW) command. During the WRITE burst, the DMI signal must be driven LOW. 7. The device requires an explicit MASKED WRITE command for all MASKED WRITE operations. The DMI signal is treated as a data mask (DM) and indicates which bytes within a burst will be masked. When the DMI signal is sampled HIGH, the device masks that beat of the burst for the given byte lane. All DQ input signals within a byte are "Don't Care" (either HIGH or LOW) when DMI is HIGH. When the DMI signal is sampled LOW, the device does not perform a MASK operation and data received on the DQ inputs is written to the array. 8. The device requires an explicit MASKED WRITE command for all MASKED WRITE operations. The device masks the write data received on the DQ inputs if five or more data bits = 1 on DQ[2:7] or DQ[10:15] (for lower byte or upper byte respectively) and the DMI signal is LOW. Otherwise, the device does not perform the MASK operation and treats it as a legal DBI pattern. The DMI signal is treated as a DBI signal, and data received on the DQ input is written to the array. 9. The DMI signal is treated as a training pattern. The device does not perform any MASK operation and does not invert write data received on the DQ inputs. 10. The DMI signal is treated as a training pattern. The device returns the data pattern written to the WRITE-FIFO. 11. The DMI signal is treated as a training pattern. For more information, see the Read DQ Calibration Training section. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 37: MASKED WRITE Command with Write DBI Enabled; DM Enabled T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 DES DES DES DES DES DES DES DES DES CK_c CK_t CKE CS CA Valid Valid Valid Valid Command MASK WRITE-1 CAS-2 t WL DQSS DQS_c DQS_t t t DQS2DQ WPRE DQ[7:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid N1 I 2 I M3 N I N M N N DMI[0] Don’t Care Notes: 1. 2. 3. 4. N: Input data is written to DRAM cell. I: Input data is inverted, then written to DRAM cell. M: Input data is masked. The total count of 1 data bits on DQ[7:2] is equal to or greater than five. Data mask (DM) is enable: MR13 OP [5] = 0, Data bus inversion (DBI) write is enable: MR3 OP[7] = 1. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 98 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 38: WRITE Command with Write DBI Enabled; DM Disabled T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 DES DES DES DES DES DES DES DES DES CK_c CK_t CKE CS CA Valid Valid Valid Valid Command WRITE-1 CAS-2 t WL DQSS DQS_c DQS_t t DQS2DQ t WPRE DQ[7:0] Valid Valid Valid N1 N Valid Valid Valid Valid Valid Valid Valid I2 I N N I N N N DMI[0] Don’t Care Notes: 1. N: Input data is written to DRAM cell. 2. I: Input data is inverted, then written to DRAM cell. 3. Data mask (DM) is disable: MR13 OP [5] = 1, Data bus inversion (DBI) write is enable: MR3 OP[7] = 1. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 99 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification WRITE and MASKED WRITE Operation DQS Control (WDQS Control) The device supports WRITE, MASKED WRITE, and WR-FIFO operations with the following DQS controls. Before and after WRITE, MASKED WRITE, and WR-FIFO operations, DQS_t, and DQS_c are required to have sufficient voltage gap to make sure the write buffers operate normally without any risk of meta-stability. The device is supported by either of the two WDQS control modes below. • Mode 1: Read-based control • Mode 2: WDQS_on/WDQS_off definition based control Regardless of ODT enable/disable, WDQS-related timing described here does not allow any change of existing command timing constraints for all READ/WRITE operations. In case of any conflict or ambiguity on the command timing constraints caused by the specification here, the specification defined in the Timing Constraints for Training Commands table should have higher priority than WDQS control requirements. To prevent write preamble related failure, either of the two WDQS controls to the device should be supported. WDQS Control Mode 1 – Read-Based Control The device needs to be guaranteed the differential WDQS, but the differential WDQS can be controlled as described below. WDQS control requirements here can be ignored while differential read DQS is operated or while DQS hands over from read to write or vice versa. 1. When WRITE/MASKED WRITE command is issued, SoC makes the transition from driving DQS_c HIGH to driving differential DQS_t/DQS_c, followed by normal differential burst on DQS pins. 2. At the end of post amble of WRITE/MASKED WRITE burst, SoC resumes driving DQS_c HIGH through the subsequent states except for DQS toggling and DQS turn around time of WT-RD and RD-WT as long as CKE is HIGH. 3. When CKE is LOW, the state of DQS_t/DQS_c is allowed to be “Don’t Care.” Figure 39: WDQS Control Mode 1 WT CMD WT BURST Following states from WT burst CKE DQS_c DQS_t Don’t Care WDQS Control Mode 2 – WDQS_On/Off After WRITE/MASKED WRITE command is issued, DQS_t and DQS_c required to be differential from WDQS_on, and DQS_t and DQS_c can be “Don’t Care” status from WDQS_off of WRITE/MASKED WRITE command. When ODT is enabled, WDQS_on and WDQS_off timing is located in the middle of the operations. When host disables ODT, WDQS_on and WDQS_off constraints conflict with tRTW. The timing does not conflict when ODT is enabled because WDQS_on and WDQS_off timing is covered in ODTLon and ODTLoff. However, regardless of ODT on/off, WDQS_on/off timing below does not change any command timing constraints for all read and write operations. To prevent the conflict, WDQS_on/off requirement can be ignored where WDQS_on/off timing is overlapped with read operCCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 100 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification ation period including READ burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD). In addition, the period during DQS toggling caused by read and write can be counted as WDQS_on/off. Parameters • WDQS_on: The maximum delay from WRITE/MASKED WRITE command to differential DQS_t and DQS_c • WDQS_off: The minimum delay for DQS_t and DQS_c differential input after the last WRITE/MASKED WRITE command • WDQS_Exception: The period where WDQS_on and WDQS_off timing is overlapped with READ operation or with DQS turn around (RD-WT, WT-RD) – WDQS_Exception @ ODT disable = MAX(WL-WDQS_on + tDQSTA - tWPRE - n tCK, 0 tCK) where RD to WT command gap = tRTW(MIN)@ODT disable + n tCK – WDQS_Exception @ ODT enable = tDQSTA Table 107: WDQS_On/WDQS_Off Definition WRITE Latency WDQS_On (Max) WDQS_Off (Min) Set A Set B nWR nRTP Set A Set B Set A Set B Lower Frequency Limit (>) Upper Frequency Limit (≤) 4 4 6 8 0 0 15 15 10 266 6 8 10 8 0 0 18 20 266 533 8 12 16 8 0 6 21 25 533 800 10 18 20 8 4 12 24 32 800 1066 12 22 24 10 4 14 27 37 1066 1333 14 26 30 12 6 18 30 42 1333 1600 16 30 34 14 6 20 33 47 1600 1866 18 34 40 16 8 24 36 52 1866 2133 Notes: 1. WDQS_on/off requirement can be ignored when WDQS_on/off timing is overlapped with READ operation period including READ burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD). 2. DQS toggling period caused by read and write can be counted as WDQS_on/off. Table 108: WDQS_On/WDQS_Off Allowable Variation Range Min Max Unit WDQS_on –0.25 0.25 tCK(avg) WDQS_off –0.25 0.25 tCK(avg) Table 109: DQS Turn-Around Parameter Parameter t DQSTA Note: 1. Description Value Unit Note Turn-around time RDQS to WDQS for WDQS control case TBD – 1 tDQSTA is only applied to WDQS_exception case when WDQS Control. Except for WDQS Control, tDQSTA can be ignored. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 101 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 40: Burst WRITE Operation T0 T1 T2 T3 BL BA0, CA,AP CA CA T4 Ta0 Ta1 Ta2 DES DES DES DES Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 Ta11 Ta12 Ta13 Ta14 Ta15 Ta16 Ta17 Ta18 Ta19 Ta20 Ta21 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 WL WDQS_off t DQSS(MIN) tWPRE WDQS_on t WPST DQS_c DQS_t t DQS2DQ DI DI DI DI n0 n1 n0 n2 n3 DQ DI DI DI DI DI DI DI DI DI DI DI DI n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 t DQSS(MAX) t t WPRE WPST DQS_c DQS_t t DQS2DQ DI n0 DI DI DI n0 n1 n2 n3 DQ ODTLon DI DI DI DI DI DI DI DI DI DI DI DI n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 tODTon(MAX) tODTon(MIN) DRAM RTT ODT High-Z Transion Transition ODT on ODTL off ODT High-Z tODToff(MIN) tODToff(MAX) Don’t Care Notes: 1. 2. 3. 4. BL=16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. DI n = data-in to column n. DES commands are shown for ease of illustration; other commands may be valid at these times. DRAM RTT is only applied when ODT is enabled (MR11 OP[2:0] is not 000b). CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 102 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 41: Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Disable) T0 T1 T2 T3 BL BA0, CA, AP CA CA T8 T4 T a0 Ta1 T a2 T a3 T a4 BL BA0, CA, AP CA CA Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 T b7 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command CAS-2 READ-1 DES DES DES CAS-2 WR-1/MWR-1 RL + RU(tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST) - WL + tWPRE t WL DQSS WDQS_off WDQS_on t RL WDQS_exception DQSCK t BL/2 = 8 t RPRE WPRE DQS_c DQS_t t D0 n0 DQ t DQSQ t RPST t DQSTA DQS2DQ DI n0 D0 D0 D0 D0 D0 D0 D0 n9 n10 n11 n12 n13 n14 n15 DI DI DI DI DI DI DI n9 n10 n11 n12 n13 n14 n15 Don’t Care Notes: 1. 2. 3. 4. BL = 16, Read preamble = Toggle, Read postamble = 0.5nCK, Write preamble = 2nCK, Write postamble = 0.5nCK. DO n = data-out from column n, DI n = data-in to column n. DES commands are shown for ease of illustration; other commands may be valid at these times. WDQS_on and WDQS_off requirement can be ignored where WDQS_on/off timing is overlapped with READ operation period including READ burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD). Figure 42: Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Enable) T0 T1 T2 T3 BL BA0, CA,AP CA CA T4 T8 Ta0 Ta1 Ta2 Ta3 Ta4 BL BA0, CA,AP CA CA Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 DES DES DES DES DES DES DES Tc2 Td0 Td1 Td2 Td3 Td4 Te0 Te1 Te2 Te3 DES DES DES DES DES DES DES DES DES Te4 Te5 Te6 Tf0 Tf1 DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES DES CAS-2 WR-1/MWR-1 DES RL + RU(tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/ tCK) + 1 DES t DQSS WL WDQS_off ODTL_off WDQS_on ODTLon t DQSCK RL t BL/2 = 8 t WPRE RPRE DQS_c DQS_t t DQ tRPST DQSQ DO n0 DO DO n9 n10 t DQSTA t DI DO DO DO DO DO n11 n12 n13 n14 n15 n0 DQS2DQ DI n9 DI DI DI DI DI ODToff,max ODTon,min DRAM RTT DI n10 n11 n12 n13 n14 n15 ODTon,max ODT High-Z Transion ODToff,min Transition ODT On Transion ODT High-Z Don’t Care Notes: 1. BL = 16, Read preamble = Toggle, Read postamble = 0.5nCK, Write preamble = 2nCK, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DO n = data-out from column n, DI n = data-in to column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 103 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification 4. WDQS_on and WDQS_off requirement can be ignored where WDQS_on/off timing is overlapped with READ operation period including READ burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD). Preamble and Postamble Behavior Preamble, Postamble Behavior in READ-to-READ Operations The following illustrations show the behavior of the device's read DQS_t and DQS_c pins during cases where the preamble, postamble, and/or data clocking overlap. DQS will be driven with the following priority 1. Data clocking edges will always be driven 2. Postamble 3. Preamble Essentially the data clocking, preamble, and postamble will be ordered such that all edges will be driven. Additional examples of seamless and borderline non-overlapping cases have been included for clarity. READ-to-READ Operations – Seamless Figure 43: READ Operations: tCCD = MIN, Preamble = Toggle, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 CAm CAm T12 T13 T14 T15 T16 T17 T18 T19 T20 T26 T27 T28 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 BL DES DES t BA0, CA, AP READ-1 CAS-2 CCD = 8 RL = 6 t RL = 6 t DQSCK DQSCK t t RPST RPRE DQS_c DQS_t High-Z High-Z t DQSQ t DQSQ DQ DMI High-Z DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 m0 m1 m12 m13 m14 m15 BL/2 = 8 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 104 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification READ-to-READ Operations – Consecutive Figure 44: Seamless READ: tCCD = MIN + 1, Preamble = Toggle, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 BL BA0, CA, AP CAm CAm T13 T14 T15 T16 T17 T18 T19 T20 T21 T26 T27 T28 T29 T30 DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES READ-1 CAS-2 CCD = 9 t RL = 6 t RL = 6 DQSCK DQSCK t t RPST RPRE t RPST DQS_c High-Z DQS_t High-Z t t DQSQ DQ DMI DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 BL/2 = 8 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 45: Consecutive READ: tCCD = MIN + 1, Preamble = Toggle, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 CAm CAm T13 T14 T15 T16 T17 T18 T19 T20 T21 T26 T27 T28 T29 T30 DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 BL DES DES t DES BA0, CA, AP READ-1 CAS-2 CCD = 9 RL = 6 t RL = 6 t DQSCK DQSCK t t RPRE t RPST RPRE t RPST DQS_c DQS_t High-Z High-Z t t DQSQ DQ DMI High-Z DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 BL/2 = 8 High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 105 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 46: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 BL BA0, CA, AP CAm CAm T13 T14 T15 T16 T17 T18 T19 T20 T21 T26 T27 T28 T29 T30 DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES READ-1 CAS-2 CCD = 9 t RL = 6 t RL = 6 DQSCK DQSCK t t RPRE t RPST RPST DQS_c High-Z DQS_t High-Z t t DQSQ DQ High-Z DMI DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 BL/2 = 8 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 47: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 CAm CAm T13 T14 T15 T16 T17 T18 T19 T20 T21 T26 T27 T28 T29 T30 DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 BL DES DES t DES BA0, CA, AP READ-1 CAS-2 CCD = 9 RL = 6 RL = 6 t t DQSCK DQSCK t t RPRE t RPRE RPST DQS_c DQS_t High-Z High-Z t t DQSQ DQ DMI High-Z DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 BL/2 = 8 High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 106 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 48: Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 BL BA0, CA, AP CAm CAm T14 T15 T16 T17 T18 T19 T20 T21 T22 T28 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES READ-1 CAS-2 CCD = 10 t RL = 6 t RL = 6 DQSCK DQSCK t t RPRE RPST t t RPRE RPST DQS_c High-Z DQS_t High-Z t DQ DQSQ DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z DMI t High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 BL/2 = 8 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 49: Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 BL BA0, CA, AP CAm CAm T14 T15 T16 T17 T18 T19 T20 T21 T22 T28 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES READ-1 CAS-2 CCD = 10 RL = 6 t RL = 6 t DQSCK DQSCK t RPRE t RPST t RPRE t RPST DQS_c DQS_t High-Z High-Z t DQ DMI High-Z t DQSQ DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 BL/2 = 8 High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 50: Consecutive READ: tCCD = MIN + 2, Preamble = Static, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 BL BA0, CA, AP CAm CAm T14 T15 T16 T17 T18 T19 T20 T21 T22 T28 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES READ-1 CAS-2 CCD = 10 t RL = 6 t RL = 6 DQSCK DQSCK t t RPRE t RPST t RPRE RPST DQS_c High-Z DQS_t High-Z t DQ DQSQ DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z DMI t High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 BL/2 = 8 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 51: Consecutive READ: tCCD = MIN + 2, Preamble = Static, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 BL BA0, CA, AP CAm CAm T14 T15 T16 T17 T18 T19 DES DES DES DES DES DES T20 T21 T22 T28 T29 T30 T31 DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES READ-1 CAS-2 CCD = 10 RL = 6 t RL = 6 t DQSCK DQSCK t RPRE t RPST t RPRE t RPST DQS_c DQS_t High-Z High-Z t DQ DMI High-Z t DQSQ DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 BL/2 = 8 High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 108 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 52: Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 T14 BL BA0, CA, AP CAm CAm T15 T16 T17 T18 T19 T20 T21 T22 T23 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES DES READ-1 CAS-2 CCD = 11 t RL = 6 t RL = 6 DES DQSCK DQSCK t t RPRE t RPST t RPRE RPST DQS_c High-Z DQS_t High-Z t DQ DQSQ DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z DMI t DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 53: Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 T14 BL BA0, CA, AP CAm CAm T15 T16 T17 T18 T19 T20 DES DES DES DES DES DES T21 T22 T23 T29 T30 T31 DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES DES READ-1 CAS-2 CCD = 11 RL = 6 t RL = 6 t DQSCK DQSCK t t RPRE t RPST RPRE t RPST DQS_c DQS_t High-Z High-Z t DQ DMI High-Z DES High-Z t DQSQ DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 BL/2 = 8 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 109 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 54: Consecutive READ: tCCD = MIN + 3, Preamble = Static, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 T14 BL BA0, CA, AP CAm CAm T15 T16 T17 T18 T19 T20 DES DES DES DES DES DES T21 T22 T23 T29 T30 T31 DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES DES READ-1 CAS-2 CCD = 11 t RL = 6 t RL = 6 DES DQSCK DQSCK t t RPRE t RPST t RPRE RPST DQS_c High-Z DQS_t High-Z t t DQSQ DQ DMI DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 55: Consecutive READ: tCCD = MIN + 3, Preamble = Static, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 T14 BL BA0, CA, AP CAm CAm T15 T16 T17 T18 T19 T20 T21 T22 T23 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES DES READ-1 CAS-2 CCD = 11 RL = 6 t RL = 6 t DES DQSCK DQSCK t t RPRE t RPST RPRE t RPST DQS_c DQS_t High-Z High-Z High-Z t t DQSQ DQ DMI High-Z DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 BL/2 = 8 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6, Preamble = Static; Postamble = 0.5nCK 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 110 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification WRITE-to-WRITE Operations – Seamless Figure 56: Seamless WRITE: tCCD = MIN, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA CAn CAn T4 T5 T6 T7 T8 T9 T10 T11 BL BA0, CA CAm CAm T12 T13 T14 T15 T16 T17 T18 T23 T24 T25 T26 T27 T28 DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES DES t DES DES WRITE-1 CAS-2 CCD = 8 WL = 4 WL = 4 t t t DQSS DQSS WPRE t WPST DQS_c DQS_t t DQS2DQ t DQS2DQ DQ DMI DIN n0 DIN DIN DIN n1 n2 n3 DIN n4 DIN DIN n5 n6 DIN n7 DIN n8 BL/2 = 8 DIN n9 DIN DIN DIN DIN DIN DIN n10 n11 n12 n13 n14 n15 DIN m0 DIN m1 DIN m2 DIN m3 DIN m12 DIN DIN DIN m13 m14 m15 BL/2 = 8 Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK. 2. DIN n/m = data-in from column n and column m. 3. The minimum number of clock cycles from the burst WRITE command to the burst WRITE command for any bank is BL/2. 4. DES commands are shown for ease of illustration; other commands may be valid at these times. CCM005-554574167-10809 z42m_embedded_lpddr4x_lpddr4.pdf - Rev. G 05/2022 EN 111 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary LPDDR4X/LPDDR4 SDRAM General LPDDR4X Specification Figure 57: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble, 533 MHz < Clock Frequency